5 Commits

Author	SHA1	Message	Date
sergei	e367ccc0ee	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names. ... * Change register type of second operand in CTC1 and CFC1 instructions to R_SPECIALREGISTER, so it is not output using a symbolic name. Mantis #26380. git-svn-id: trunk@28034 -	2014-06-22 22:01:44 +00:00
sergei	c260879439	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). ... * cpubase.pas, std_regname: changed logic to lookup known names for special registers before resorting to default name, so that $fcc0..$fcc7 can be used as operands. git-svn-id: trunk@27992 -	2014-06-17 23:15:34 +00:00
florian	de4a96f96d	* fixes several register allocation related mips issues ... * fixes range check error in mips code git-svn-id: trunk@20266 -	2012-02-05 21:58:45 +00:00
florian	3d2a27c66c	* fix fpu register type ... git-svn-id: trunk@20261 -	2012-02-05 09:14:55 +00:00
florian	f58fcdf401	+ basic mips stuff	2005-02-13 18:56:44 +00:00