so it also works for 32 bit targets and a high level code generator
(where aint is still 32 bit, but 64 bit operations are not decomposed)
git-svn-id: trunk@41441 -
(cherry picked from commit 07bd4ba517)
With local change to fix compilation for x86_64 CPU
40307
40309
40314
40319
40322
40324
40326
40377
40378 from trunk to fixes_3_2
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r40277 | pierre | 2018-11-08 20:18:30 +0000 (Thu, 08 Nov 2018) | 1 line
Implement mark_write override for tinilinenode
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--- Merging r40277 into '.':
U compiler/ninl.pas
--- Recording mergeinfo for merge of r40277 into '.':
U .
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r40307 | pierre | 2018-11-13 15:10:21 +0000 (Tue, 13 Nov 2018) | 6 lines
+ Introduce PPC_SUFFIXES, new make variable that lists all ppc suffixes
for all different CPUs supported.
* Use PPC_SUFFIXES in execlean and CPU_clean targets.
* Also delete CPU/bin subbirectory.
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--- Merging r40307 into '.':
U compiler/Makefile
U compiler/Makefile.fpc
--- Recording mergeinfo for merge of r40307 into '.':
G .
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r40309 | pierre | 2018-11-13 15:51:32 +0000 (Tue, 13 Nov 2018) | 1 line
Try to avoid expectloc not set after first pass error for call node
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--- Merging r40309 into '.':
U compiler/ncal.pas
--- Recording mergeinfo for merge of r40309 into '.':
G .
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r40314 | pierre | 2018-11-14 13:13:19 +0000 (Wed, 14 Nov 2018) | 4 lines
* Change first parameter type of function is_continuous_maks to aword type.
Add typecasts where needed to allow for successful compilation of arm-linux target
with -CriotR options when building the compiler.
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--- Merging r40314 into '.':
U compiler/arm/cpubase.pas
U compiler/arm/cgcpu.pas
--- Recording mergeinfo for merge of r40314 into '.':
G .
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r40319 | pierre | 2018-11-15 16:58:40 +0000 (Thu, 15 Nov 2018) | 1 line
Disable range check in m68k:tiscv32 and riscv64 cgcpu units
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--- Merging r40319 into '.':
C compiler/riscv64
U compiler/m68k/cgcpu.pas
C compiler/riscv32
--- Recording mergeinfo for merge of r40319 into '.':
G .
Summary of conflicts:
Tree conflicts: 2
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r40322 | pierre | 2018-11-15 22:01:25 +0000 (Thu, 15 Nov 2018) | 1 line
Also disable range checking in arm/aoptcpu unit
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--- Merging r40322 into '.':
U compiler/arm/aoptcpu.pas
--- Recording mergeinfo for merge of r40322 into '.':
G .
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r40324 | pierre | 2018-11-16 10:27:42 +0000 (Fri, 16 Nov 2018) | 4 lines
* Disable range check for m68k/aoptcpu unit
* Add missing change of var parameter p to next instruction
in TryToOptimizeMove method after instruction removal.
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--- Merging r40324 into '.':
U compiler/m68k/aoptcpu.pas
--- Recording mergeinfo for merge of r40324 into '.':
G .
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r40326 | pierre | 2018-11-16 13:28:26 +0000 (Fri, 16 Nov 2018) | 1 line
Change local variables offsetdec and extraoffset type to ASizeInt
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--- Merging r40326 into '.':
U compiler/ncgmem.pas
--- Recording mergeinfo for merge of r40326 into '.':
G .
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r40377 | pierre | 2018-11-27 10:19:36 +0000 (Tue, 27 Nov 2018) | 1 line
Fix bug report 34605 and add corresponding test
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--- Merging r40377 into '.':
A tests/webtbs/tw34605.pp
U compiler/nutils.pas
--- Recording mergeinfo for merge of r40377 into '.':
G .
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r40378 | pierre | 2018-11-27 10:21:37 +0000 (Tue, 27 Nov 2018) | 1 line
Avoid range errors or overflows on for AVR cpu, when computing address offsets
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--- Merging r40378 into '.':
U compiler/ncgset.pas
U compiler/ngtcon.pas
--- Recording mergeinfo for merge of r40378 into '.':
G .
git-svn-id: branches/fixes_3_2@40716 -
from cpubase unit to a method in the tcg class. The reason for doing that is
that this is now a standard part of the 16-bit and 8-bit code generators and
moving to the tcg class allows doing extra checks (not done yet, but for
example, in the future, we can keep track of whether there was an extra
register allocated with getintregister and halt with an internalerror in case
GetNextReg() is called for registers, which weren't allocated as a part of a
sequence, therefore catching a certain class of 8-bit and 16-bit code
generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
anything. It might be added to the tcg class, in case it's ever needed, but
for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.
git-svn-id: trunk@37180 -
already in a register, as this changes the result location into a size
different from what resultdef says (and only in that specific case)
o modified the ppc code so that it always forces a setelementn to uinttype,
as that is the size that is expected by the operations later on
git-svn-id: trunk@32296 -
labels of LOC_JUMP in the node's location. This generates some extra jumps
for short circuit boolean and/or-expressions if optimizations are off, but
with optimisations enabled the generated code is the same (except for JVM
because the jump threading optimisation isn't enabled there yet).
git-svn-id: trunk@31431 -
future use by high level code generator targets
o this in turn required that all a_load*_loc* methods are called via
hlcg rather than via cg, since a location can be a subsetref/reg and
and those are no longer handled in tcg
o that then required moving several force_location_* routines into
thlcg because they use a_load_loc*, but did not take tdef size
parameters (which are required by the thlcg a_load_loc* routines)
o the only practical consequence is that from now on, you have to
use hlcg.location_force_mem/reg() (fpureg not yet) and
hlcg.gen_load_loc_cgpara() instead of the removed versions from ncgutil,
and hlcg.a_load*loc*() instead of cg.a_load*loc* if a subsetref/reg
might be involved
git-svn-id: trunk@21287 -
o sets of enums are handled as JUEnumSet instances, others as JUBitSet
derivatives (both smallsets and varsets, to make interoperability with
Java easier)
o special handling of set constants: these have to be constructed at run
time. In case of constants in the code, create an internal constsym to
represent them. These and regular constsyms are then aliased by an
another internal staticvarsym that is used to initialise them in the
unit initialisation code.
o until they are constructed at run time, set constants are encoded as
constant Java strings (with the characters containing the set bits)
o hlcgobj conversion of tcginnode.pass_generate_code() for the genjumps
part (that's the only part of the generic code that's used by the JVM
target)
o as far as explicit typecasting support is concerned, currently the
following ones are supported (both from/to setdefs): ordinal types,
enums, any other set types (whose size is the same on native targets)
o enum setdefs also emit signatures
o overloading routines for different ordinal set types, or for different
enum set types, is not supported on the JVM target
git-svn-id: branches/jvmbackend@18662 -
only JVM constructs that are already implemented, but also ones that
will be supported in the future but that aren't implemented yet (to
make it easier to already adapt code to the future changes)
git-svn-id: branches/jvmbackend@18498 -
o changed type of opsize field of tcgcasenode from tcgsize into tdef,
and fixed compilation of other code generator units after this change
git-svn-id: branches/jvmbackend@18339 -
a) cpu64bitaddr, which means that we are generating a compiler which
will generate code for targets with a 64 bit address space/abi
b) cpu64bitalu, which means that we are generating a compiler which
will generate code for a cpu with support for 64 bit integer
operations (possibly running in a 32 bit address space, depending
on the cpu64bitaddr define)
All cpus which had cpu64bit set now have both the above defines set,
and none of the 32 bit cpus have cpu64bitalu set (and none will
compile with it currently)
+ pint and puint types, similar to aint/aword (not pword because that
that conflicts with pword=^word)
* several changes from aint/aword to pint/pword
* some changes of tcgsize2size[OS_INT] to sizeof(pint)
git-svn-id: trunk@10320 -
