private_extern (or plain global in case of PECOFF, as the effect is
the same there): visible across object files, but they become local
when linked into a binary/library. This enables cross-unit inlining
of functions accessig implementation-only symbols.
git-svn-id: trunk@42340 -
+ tai_const has a new field fixed_size which is used to fix the size of an s/uleb128. This is needed to ensure convergence during assembling when calculating offsets
git-svn-id: branches/debug_eh@42255 -
+ support of new alignment control values for GNU AS writer
+ support of new alignment control values for binary writer
* better alignment settings on i386-win32
* improved inserted align directives for if nodes
git-svn-id: trunk@40159 -
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.
git-svn-id: branches/laksen/riscv_new@39762 -
compiler's internal assembly representation. It is not yet generated by the
compiler and is only implemented properly in the NASM writer (but will
eventually be implemented in the other assembler writers as well, including
the internal assembler). In the future, it is intended to allow:
1) catching instructions, generated by the compiler and not supported by the
target CPU, due to a bug in the code generator
2) allowing a different instruction set to be used in inline asm blocks (I'm
planning a new directive for that - {$asmcpu XXX}), because the code
generator will be able to switch target CPU in the middle of the asm output
stream
git-svn-id: trunk@33121 -
- Fixed access to symbols with offset.
- Always use register R9 for GOT pointer to prevent bugs when free register limit is reached in a function.
- GOT is not needed for function calls by name.
git-svn-id: trunk@31681 -
that we can use assembler writers with different conventions from the
currently set target_asm (e.g. an x86 assembler writer for inline assembly
in LLVM IR)
git-svn-id: trunk@31628 -
* generate code to load the TOC register if it's required, and
emit the the ".localentry" directive to indicate to the linker
where the actual function body starts
* support the ".localentry" directive in the ppc64 assembler reader
o disable the fpc_qword_to_double() assembler implementation for
ELFv2, because we can't manually insert the .localentry directive
before the stack allocation code
* perform indirect calls on ppc64 via R12 in ncgcal, as R12 needs to
contain the function address on entry on ppc64/ELFv2 (and it's
a volatile register, so there's no problem with always using
it)
git-svn-id: trunk@30198 -
names, and disabled them for ppc64 ELFv2
* disabling those also disables the function descriptors, so use the
_CALL_ELF compiler variable to check whether there is in fact a
function descriptor
git-svn-id: trunk@30196 -
to free up space for more ait_* types in taitype (can't have
more than 32 because they have to fit in a small set)
o factored out writing of floating point numbers as an array of
byte in the external assemblers
git-svn-id: branches/hlcgllvm@28105 -
the value set by -Ch or the second parameter to the $M directive). This is
equivalent to the heapmin value in Turbo Pascal 7 and ensures that the program
has at least this amount of heap space available (otherwise DOS will show a
'not enough memory' error and will refuse to load the program).
git-svn-id: trunk@28002 -
itself (instead of having a fixed 16k stack in the startup code). This allows
setting the stack size in these models with the -Cs option.
git-svn-id: trunk@27820 -
otherwise data in initialised packed records gets aligned wrongly. This
should probably also be done for other targets that automatically
align .short/.long/...
git-svn-id: trunk@27600 -
Add support for .set and .weak on AVR.
Fix 64 bit negation on AVR.
Add cpu_capabilities to cpuinfo.pas and fixed some peephole optimizations.
Pass >4 byte parameters by reference.
git-svn-id: trunk@26943 -
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.
git-svn-id: trunk@26886 -
* aggas.pas, TGNUAssembler.WriteTree.doalign:
instead of strangely checking for the previous instruction always use .balignw if the previous code was code and we should not use a specific instruction
git-svn-id: trunk@26839 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
So we need to do this manually by changing (in that case) from ".balign" to ".balignw" and passing the opcode of the "NOP" instruction as a argument. The Coldfire manual suggests here to use the "TPF" instruction, but somehow QEMU does not interpret that correctly.
aggas.pas, tgnuassembler.writetree:
* keep track of the last "tai" and pass that to "doalign"
* doalign: do the special handling mentioned above for m68k
git-svn-id: trunk@22799 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
o the order of .lcomm operands was inverted and can't specify an alignment
o the section in which to place them can't be adorned using [RW] access
specifiers (it's always in .bss, which is [RW] by definition)
git-svn-id: trunk@22644 -
