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439 Commits

Author SHA1 Message Date
ccrause
b0003f71dd Check rjmp destination range. 2025-03-02 19:50:30 +02:00
florian
7878a7b390 * better error reporting 
* indentation
 2025-03-02 14:58:48 +01:00
ccrause
a43f1bc1d0 Change branch and jump destinations to byte based distances. 2025-03-02 14:43:33 +02:00
florian
a685e2aa5a + avrsim6 controller type 2024-09-14 16:00:35 +02:00
florian
761b451962 + AVR: dummy thlcgcpu.g_intf_wrapper implementation 2024-09-14 16:00:07 +02:00
florian
1ed9054bb9 * fix capabilites check 2024-09-10 22:53:35 +02:00
florian
f49da05633 * unified g_concatcopy_move 2024-05-15 22:52:24 +02:00
florian
e7716dc05f + avr: overflow checking for abs, together with the other recent abs-related commits, resolves #40694 2024-04-02 19:01:42 +02:00
ccrause
dd858f37aa Ensure register to be eliminated is de-allocated before applying optimization LdsMov2Lds. 2024-03-24 13:54:31 +00:00
Michaël Van Canneyt
a15dfba971 * Fix compilation 2024-03-05 07:56:14 +00:00
ccrause
248082347f AVR optimization LdsMov2Lds 2023-12-02 18:22:35 +00:00
ccrause
be54d40660 Also add boot information to board aliases. 2023-05-22 19:08:01 +00:00
ccrause
289fdc72c5 [AVR] Include bootloader starting address and max size where relevant. 2023-05-22 19:08:01 +00:00
ccrause
f83a8f0f8f Only perform OpCp2Op optimization when the first Op is ANDI and comparison is against 0. 2023-03-09 18:19:20 +02:00
florian
a221f2af79 * completed post/pre inc/decrement addressing mode instructions in TAoptBaseCpu.RegModifiedByInstruction 2023-02-18 11:15:39 +01:00
florian
22f1289b2a * post/pre inc/decrement references modify obviously the base register on avr, resolves #40153 2023-02-17 23:02:40 +01:00
ccrause
7822a90e20 Increase reference count of jump label, fixes #39784 2022-06-18 12:28:36 +00:00
florian
e28b76a64e * avr tiny has no adiw/sbiw instructions, resolves #39783 2022-06-16 23:01:47 +02:00
florian
bce88f2e2b * AVR: trgcpu.do_spill_read must load ofs 2022-05-05 19:35:38 +02:00
florian
0ae45bd2cf + AVR: track flag usage 
+ AVR: take care of allocated flags when spilling
  * AVR: trgcpu.do_spill_read might also use ADIW
 2022-05-01 22:42:57 +02:00
florian
038230bbea * AVR: use adiw to create spilling constants if possible 
* AVR: insert allocations for registers used by spilling so the assembler optimizer does not remove spilling code
 2022-05-01 22:42:57 +02:00
florian
46b52d92d3 + AVR: helpers take care of ADIW 2022-05-01 22:42:57 +02:00
florian
5d97ff43fa + CPUAVR_HAS_ADIW 2022-04-29 23:06:17 +02:00
florian
314d3579fc * avr3 and avr31 should also have a movw instruction 2022-04-29 23:06:17 +02:00
florian
33eef1f9b1 * AVR: moved MovMov2Movw optimization into pass2 as it might prevent other optimizations 2022-04-25 22:18:37 +02:00
florian
9695dba4d9 * AVR: fix TCpuAsmOptimizer.InstructionLoadsFromReg for MOVW 
* simplify code for MovMov2Movw optimization
 2022-04-24 22:42:09 +02:00
florian
49edb0b606 * AVR: fix TAoptBaseCpu.RegModifiedByInstruction, resolves #39623 2022-04-24 22:41:10 +02:00
florian
e87c52d7dc * otherwise => else 2022-04-24 22:40:07 +02:00
ccrause
6df2eb5fd4 Extra code generation options for shift with compile time constant. 2022-03-30 20:48:52 +00:00
florian
27fb9086aa * cleanup: cs_opt_loopunroll is a generic optimization for a long time already 2022-03-08 23:03:18 +01:00
florian
6f749cf43d * first part to fix #39603 2022-02-27 23:20:07 +01:00
florian
ff3acfb8cd * cleanup of 2.7.0 defines 2021-10-31 13:20:28 +01:00
florian
c28995494c * reverted wrongly committed file 2021-09-01 09:31:14 +02:00
florian
9526fc64cd + Aarch64: FMovFMov2FMov 2 optimization 2021-09-01 09:31:14 +02:00
florian
7a8893396d * revert last commit, avr4 has no call/jmp 
git-svn-id: trunk@49620 -
 2021-07-18 21:47:22 +00:00
florian
eb96734b20 * avr4 has mul instructions 
git-svn-id: trunk@49619 -
 2021-07-18 21:41:57 +00:00
florian
aec49340a3 * patch by Christo Crause, resolves #38961, fixes the following formatting and spelling problems in the AVR compiler files: 
- Change spelling of AM_PREDRECEMENT to AM_PREDECREMENT
    - Fix multiline comment style to use {}
    - Fix indenting of code in method tcgavr.g_concatcopy

git-svn-id: trunk@49474 -
 2021-06-04 20:16:25 +00:00
florian
9d6ceda532 * patch by Christo Crause: do not generate LDD for avrtiny, resolves #38958 
git-svn-id: trunk@49473 -
 2021-06-03 18:48:40 +00:00
florian
c43d8e4adf * indention fixed 
git-svn-id: trunk@49379 -
 2021-05-18 19:13:49 +00:00
florian
430b2fd791 * AVR: second part of assembler optimizer rework 
git-svn-id: trunk@49378 -
 2021-05-18 19:13:13 +00:00
florian
6f1d965dac * first part of AVR assembler optimizer reword 
git-svn-id: trunk@49377 -
 2021-05-17 20:02:12 +00:00
florian
bc21634b46 * AVR: made avr_des intrinsic more usefull 
git-svn-id: trunk@49362 -
 2021-05-13 18:59:28 +00:00
florian
022a9b210f + AVR: avr_des intrinsic 
git-svn-id: trunk@49353 -
 2021-05-13 09:26:53 +00:00
florian
9bfc731bb6 + AVR: MovOp2Op 2 optimization 
git-svn-id: trunk@49350 -
 2021-05-12 19:20:10 +00:00
florian
5e1e6c24a4 * patch by Christo Crause: handle references to absolute address 0 correctly, resolves #38861 
git-svn-id: trunk@49344 -
 2021-05-07 16:19:05 +00:00
florian
05cf47f995 * AVR: fixed TCpuAsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@49126 -
 2021-04-06 11:49:48 +00:00
yury
4fa99cff62 * Removed more assigned but unused vars. 
git-svn-id: trunk@48392 -
 2021-01-24 14:05:21 +00:00
yury
0a021be803 * Corrected visibility of overridden methods. 
git-svn-id: trunk@48385 -
 2021-01-24 12:41:12 +00:00
yury
64c586b86d * Removed/ifdefed lots of unused variables. 
git-svn-id: trunk@48384 -
 2021-01-24 12:24:01 +00:00
florian
3482121831 * patch by Christo Crause: Fix missed optimization opportunities, resolves #38285 
git-svn-id: trunk@47925 -
 2020-12-31 15:33:39 +00:00