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4 Commits

Author SHA1 Message Date
Pierre Muller
6f3582954c Use same features for riscv32 as for arm and xtensa CPUs 2023-05-23 22:39:03 +02:00
pierre
546a679f4e Add -SfPROCESSES for arm cpu, to be able to compile fcl-base package as for xtensa 
git-svn-id: trunk@45968 -
 2020-07-30 14:22:05 +00:00
florian
702e63e59f * build more units for FreeRTOS 
git-svn-id: trunk@44838 -
 2020-04-19 08:41:30 +00:00
florian
391512546e + initial FreeRTOS RTL support, largely based on the Embedded target, limited to Xtensa so far 
git-svn-id: trunk@44400 -
 2020-03-29 17:13:45 +00:00