+ RTL support:
o VFP exceptions are disabled by default on Darwin,
because they cause kernel panics on iPhoneOS 2.2.1 at least
o all denormals are truncated to 0 on Darwin, because disabling
that also causes kernel panics on iPhoneOS 2.2.1 (probably
because otherwise denormals can also cause exceptions)
* set softfloat rounding mode correctly for non-wince/darwin/vfp
targets
+ compiler support: only half the number of single precision
registers is available due to limitations of the register
allocator
+ added a number of comments about why the stackframe on ARM is
set up the way it is by the compiler
+ added regtype and subregtype info to regsets, because they're
also used for VFP registers (+ support in assembler reader)
+ various generic support routines for dealing with floating point
values located in integer registers that have to be transferred to
mm registers (needed for VFP)
* renamed use_sse() to use_vectorfpu() and also use it for
ARM/vfp support
o only superficially tested for Linux (compiler compiled with -Cpvfpv6
-Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
the fpu exception handler still needs to be implemented), Darwin has
been tested more thoroughly
+ added ARMv6 cpu type and made it default for Darwin/ARM
+ ARMv6+ implementations of atomic operations using ldrex/strex
* don't use r9 on Darwin/ARM, as it's reserved under certain
circumstances (don't know yet which ones)
* changed C-test object files for ARM/Darwin to ARMv6 versions
* check in assembler reader that regsets are not empty, because
instructions with a regset operand have undefined behaviour in that
case
* fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
int64->single type conversion
* fixed constant pool locations in case 64 bit constants are generated,
and/or when vfp instructions with limited reach are present
WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
code with -Cparmv6 (or higher), or you will get crashes. The reason is
that storing/restoring multiple VFP registers must happen using
different instructions on pre/post-ARMv6.
git-svn-id: trunk@14317 -
alignment for each memory reference (mantis #12137, and
test/packages/fcl-registry/tregistry1.pp on sparc). This also
enables better code generation for packed records in many cases.
o several changes were made to the compiler to minimise the chances
of accidentally forgetting to set the alignment of memory references
in the future:
- reference_reset*() now has an extra alignment parameter
- location_reset() can now only be used for non LOC_(C)REFERENCE,
use location_reset_ref() for those (split the tloc enum so the
compiler can catch errors using range checking)
git-svn-id: trunk@12719 -
shortstring temps don't get maximum alignment)
* changed some gettemptyed() calls into gettemp() calls (gettemptyped
means that this temp can only be used for temps of that type,
which is necessary for refcounted types but not for floats)
git-svn-id: trunk@12036 -
- Explicit typecasts like LongBool(byte_value) do not change ordinal value.
- Explicit typecasts like ByteBool(longint_value) do not change ordinal value and can lead to data loss if longint_value is outside of ByteBool range.
- Explicit typecasts like ByteBool(LongBool) handle type ranges correctly.
- Updated test tw10233.pp. It is passed by Delphi as well.
git-svn-id: trunk@10672 -
* Fixed sign/zero-extension in second_int_to_bool for all CPUs. x86 and pppc were not affected by this bug, but I fixed it for all CPUs for consistency.
* cg/tcnvint1 is passed on arm now.
git-svn-id: trunk@10669 -
size must happen without any mangling of the value (mantis #11027)
* moved checking for signed-to-unsigned (or vice versa) type
conversions in assignments from htypechk to ncnv (where there
was already code for similar checks) and added support for
bool_to_bool there as well
git-svn-id: trunk@10521 -
a) cpu64bitaddr, which means that we are generating a compiler which
will generate code for targets with a 64 bit address space/abi
b) cpu64bitalu, which means that we are generating a compiler which
will generate code for a cpu with support for 64 bit integer
operations (possibly running in a 32 bit address space, depending
on the cpu64bitaddr define)
All cpus which had cpu64bit set now have both the above defines set,
and none of the 32 bit cpus have cpu64bitalu set (and none will
compile with it currently)
+ pint and puint types, similar to aint/aword (not pword because that
that conflicts with pword=^word)
* several changes from aint/aword to pint/pword
* some changes of tcgsize2size[OS_INT] to sizeof(pint)
git-svn-id: trunk@10320 -
for qwordbool) + test:
o assigning true to such a variable now sets them to $ff/$ffff/$ffffffff
o these types are now all signed
o converting an integer type to a byte/word/long/qwordbool using an
explicit type cast keeps the integer's original value stored in the
bool, instead of forcing it to ord(true)/ord(false)
(mantis #10233 and #10613, implemented for all architectures, testsuite
tested for ppc32, sparc and x86)
* fixed some places where the rtl depended on longbool(true) having the
value 1
* extended several boolean tests (and adapted some to no longer assume
that byte/word/long/qwordbool(true)=1)
+ support for converting to qwordbool in second_int_to_bool for x86, ppc
and sparc
git-svn-id: trunk@9898 -
* small cleanups of unused variables in firstpass
* node_resources_fpu() created to get an approximation of the
required fpu registers
* for the moment use node_complexity in the CG until the
node_resource_int() is created
git-svn-id: trunk@8655 -
* symtables based on TFPHashObjectList and TFPObjectList
* rename torddef.typ to torddef.ordtype
* rename tfloatdef.typ to tfloatdef.floattype
* rename tdef.deftype to tdef.typ
* remove obsolete browser code, browcol is kept so the ide
can still be compiled
git-svn-id: trunk@5192 -
getjumplabel and added type para to getlabel for specific types
* moved lineinfo generation from assemble and aggas to dbgstabs
git-svn-id: trunk@1120 -
+ refaddr to treference added
+ refsymbol to treference added
* top_local stuff moved to an extra record to save memory
+ aint introduced
* tppufile.get/putint64/aint implemented
* tregisteralloctor renamed to trgobj
* removed rgobj from a lot of units
* moved location_* and reference_* to cgobj
* first things for mmx register allocation
