after all, although for some reason the problems only showed up with the
external assembler on x86-64 platforms other than Darwin. Now we never use
GOT entries on x86-64 anymore for local symbols, regardless of their nature,
and instead use plain RIP-relative addressing for them.
git-svn-id: trunk@21924 -
the drawback of this is that get_caller_frame and get_caller_addr might not work
anymore because they make the wrong assumption (i.e. not required by the abi)
that ebp contains always a valid (not necessarily the current) frame pointer
git-svn-id: trunk@21918 -
Like MOV these instructions support 2 operands, with the second beeing a
shifterop.
Without this patch the asm reader would fail on something like
cmp r0, r1, lsr 16
with
Error: Unknown identifier "LSR"
git-svn-id: trunk@21911 -
used across multiple levels of inheritance such as on MIPS (and the code
has to be reusable for a_call_ref/reeg in the future anyway)
git-svn-id: trunk@21906 -
defines INTERNAL_BACKTRACE (which assumes get_frame to be internal rather
than a system unit procedure)
* changed fpc_assert() declaration for jvm to be the same as for other
targets, so the same code can be used to call it in ninl now that's
called from the first pass
git-svn-id: trunk@21903 -
ARM can not reference an arbitrary offset so it needs some special
handling if the offset goes beyond abs(4095).
The code for do_spill_read and do_spill written used to be very similar.
I've partially factored out the code into spilling_create_load_store.
The former code loaded the offset from a constant pool, which is a waste
of memory-bandwidth and cache lines. The new code tries to find a way to
adjust the baseregister so the memory location can be reached more
easily, this allows us to handle at least +-1MB with just a single
additional ADD or SUB instruction. If that fails we'll resort to the normal
constant loading code, which on it's own will fallback to loading the
constant from a constant-pool.
So instead of:
ldr r1, =16388
ldr r0, [r13, r1]
which will at least uses 4 cycles (2 Instruction cycles + 2 stall
cycles) on most cores.
We try to generate:
add r1, r13, #16384
ldr r0, [r1, #4]
which most armv5+ cores will execute in 2 cycles. We'll also save on
DCache usage.
git-svn-id: trunk@21889 -
knows that the frame pointer needs to be available (and the code is also
much simpler this way), fixes test/units/system/tassert7 after r21843
git-svn-id: trunk@21869 -
If the needed adjustment is not expressible in a shifterconst, the old code
loaded a temporary register (fixed to r12) via a_load_const_reg and used it
to adjust the SP. Resulting in:
mov r12, #44
orr r12, r12, #4096
sub sp, sp, r12
The new code will try to split the adjustment into 2 shifterconstants and
will do two seperate adjustments:
sub sp, sp, #44
sub sp, sp, #4096
If that doesn't work we'll fall back to the old code. But that should
happen VERY rarely, only for stacks bigger than 256k which are not
expressible in 2 shifter constants.
git-svn-id: trunk@21863 -
result location (NR_FUNCTION_RESULT_REG is not valid on all platforms)
o this requires passing the forced function result type (if any) to this
method
o a generic, basic thlcg.a_call_name() is now available that sets the
function result location; can be called by descendants
* the availability under all circumstances of the correct function return
type enables g_call_system_proc() on the JVM platform to now determine
by itself how many stack slots are removed by the call -> do so, instead
of manually counting them (or forgetting to do so and messing up the
maximum evaluation stack height calculations)
git-svn-id: trunk@21862 -
method by one with a lower visibility, because calling the overriding
method results in a java.lang.AbstractMethodError in that case
git-svn-id: trunk@21839 -
psub.pas: Use new fpc_compiler_has_fixup_jmps conditional.
mips/aasmcpu.pas: MIPS specific fixup_jmps function,
The insttruction distance calculation is not exact as
some pseudo-instruction can be expanded to a variable number of real instructions
real calculation would only be possible if we first
convert pseudo-instuctions to real instructions before calling fixup_jmps.
ncgutil.pas: Revert commit r21791
ncgcon.pas: Revert commit r21786
mips/cgcpu.pas: Partial revert of commit r21798, no need to always use A_J,
as fixup_jmps now handles out of range branches.
git-svn-id: trunk@21822 -
The old code forced dst and src to be the same, which is highly x86
specific and creates bad register utilization on other architectures
like arm.
The new version will use more imaginary registers, allowing the register
allocator to do a better job.
I've merged second_sar and second_rox into a single procedure
second_rox_sar because they were very similar.
git-svn-id: trunk@21809 -
RegInOp did not check for a register beeing part of a shifterop
(op.shifterop^.rs) which could result in trashed registers (But that did
not seem to happen yet anyway).
I've also implemented support for top_regset, but it is currently not
generated outside of proc_entry/proc_exit anyway.
git-svn-id: trunk@21808 -
This removes the duplications in a_op_reg_reg_reg_checkoverflow.
OP_ROL stays seperate because it needs some special treatment again.
The code for OP_ROL was changed, previously it generated:
mov tempreg, #32
sub src1, tempreg, src1
mov dst, src2, ror src1
This would trash src1, which MIGHT be a problem, but i'm not totally
sure. But the mov/sub was replaced with rsb, so the new code looks like
this.
rsb tempreg, src1, #32
mov dst, src2, ror tempreg
If src1 gets freed afterwards the regallocator should be able to change
that into:
rsb src1, src1, #32
mov dst, src2, ror src1
git-svn-id: trunk@21804 -
The previous code was full with duplicated code, this new version just
maps the OP_* to the correct SM_* and does some special handling for
OP_ROL which is done via OP_ROR.
git-svn-id: trunk@21801 -
