J. Gareth "Curious Kit" Moreton
|
a907eb49c9
|
* a64: Several secondary peephole optimizations that clean up CSEL instructions
|
2024-03-15 18:08:37 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
ef1cb852a8
|
* a64: New CSEL block optimisations ported over from x86 CMOV block optimisations
|
2024-03-15 18:08:37 +00:00 |
|
Michaël Van Canneyt
|
4e8b1cb97a
|
* Fixed signature of insert_init_final_table
|
2024-03-05 07:56:14 +00:00 |
|
florian
|
a71cc71585
|
+ function needs_check_for_fpu_exceptions to unify fpu exception handling
|
2024-02-13 17:42:21 +01:00 |
|
florian
|
3ed5a4a022
|
+ when calling FPC_THROWFPUEXCEPTION in a sub routine, pi_do_call must be set, fixed for aarch64
|
2024-02-12 23:25:35 +01:00 |
|
J. Gareth "Curious Kit" Moreton
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bf29f2051c
|
* arm/a64: Added new TST post-peephole optimisation to replace previous AND/CMP/B(c) optimisation
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2024-02-11 21:39:19 +00:00 |
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J. Gareth "Curious Kit" Moreton
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b18c10d0d8
|
* arm/a64: New "OptPass2TST" routine to catch "TST; B.c; AND -> ANDS; B.c" optimisation
|
2024-02-11 21:39:19 +00:00 |
|
J. Gareth "Curious Kit" Moreton
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9f19f582c4
|
* arm/a64: New AND/CMP -> TST or ANDS optimisation
|
2024-02-11 21:39:19 +00:00 |
|
J. Gareth "Curious Kit" Moreton
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38d2f3d58c
|
* a64: Renamed OptPostCMP/And to PostPeepholeOptCMP/AND for internal consistency
|
2024-02-11 21:39:19 +00:00 |
|
J. Gareth "Curious Kit" Moreton
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72081c803e
|
* a64: SkipAligns calls removed.
|
2023-12-29 14:17:08 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
afe2e80673
|
* a64: Node parser now attempts to directly create BIC, ORN and EON instructions
|
2023-11-08 21:07:00 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
23e514621d
|
* a64: Corrected supported shifter/extender mnemonics for arithmetic/logical instructions
|
2023-10-22 13:13:58 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
bb2e626fc3
|
* a64: Fixed bug where BIC instructions were treated as having 2 operands rather than 3
|
2023-10-22 13:13:58 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
82a8640111
|
* a64: New conditional branch to CSET peephole optimisation
|
2023-10-22 12:16:50 +00:00 |
|
florian
|
657f3c52bf
|
* according to Jonas iOS doesn't zero extend results in the callee either, so check removed
|
2023-09-12 23:05:48 +02:00 |
|
florian
|
a517ada539
|
* on aarch64-darwin, the unused part of function results is not cleared
|
2023-09-10 19:27:21 +02:00 |
|
Pierre Muller
|
5a123d33ba
|
Add -Awin64-as option for aarch64 compiler for win64 target
|
2023-05-26 11:15:55 +00:00 |
|
Dmytro Bogatskyy
|
327aac7f24
|
Add aarch64-iphonesim target
|
2023-03-27 18:45:00 +00:00 |
|
florian
|
dfb8794d4d
|
* compilation after merge fixed
|
2023-01-25 20:44:34 +01:00 |
|
Pierre Muller
|
aaa6f0d9c5
|
Only signed extension is needed
|
2023-01-25 19:36:45 +00:00 |
|
Pierre Muller
|
4793447be1
|
Add sign extension to 32-bit for unaligned OS_8 and OS_16 types (to try to solve #40102)
|
2023-01-25 19:36:45 +00:00 |
|
Pierre Muller
|
cd8aa3f0e0
|
Avoid generation of invalid 'cb(n)z sp,label' instruction
|
2023-01-02 18:22:49 +00:00 |
|
florian
|
4430422489
|
* improve module local data accesses by avoiding a got read
|
2022-12-28 22:05:23 +01:00 |
|
Jonas Maebe
|
851af5033f
|
Darwin/AArch64: adjust alignment info of custom-aligned paralocs
Resolves #40019
|
2022-12-06 21:46:26 +01:00 |
|
Jonas Maebe
|
230142e183
|
AArch64 cgcpu: add missing brackets around and/or expression
|
2022-12-03 21:17:18 +01:00 |
|
Jonas Maebe
|
cd8ddffe42
|
AArch64: X18 is not a volatile register
It may be unused on some platforms, but in general it's reserved for OS library
usage (usually related to TLS)
|
2022-10-29 14:24:37 +02:00 |
|
florian
|
3a11ee9a14
|
* apply OptPass1Data to neg as well
|
2022-09-06 21:42:29 +02:00 |
|
florian
|
5cbb36f218
|
* factor out TARMAsmOptimizer.USxtOp2Op
|
2022-09-03 19:21:28 +02:00 |
|
florian
|
ed7b0c5e68
|
* AArch64: extended SxtwMov2Data to CMP and CMN
|
2022-09-03 19:03:48 +02:00 |
|
florian
|
ad1c19864d
|
* small refactoring
|
2022-09-01 21:44:18 +02:00 |
|
florian
|
9adcc891cf
|
+ Aarch64: SxtwOp2Op optimization
|
2022-09-01 21:44:18 +02:00 |
|
florian
|
29495c9ba5
|
* refactor TCpuAsmOptimizer.OptPass1SXTW
|
2022-09-01 21:44:18 +02:00 |
|
florian
|
fd94b6db91
|
* fix for TCpuAsmOptimizer.OptPass1SXTW
|
2022-08-31 20:43:49 +02:00 |
|
florian
|
8a0498622b
|
+ AArchz64: TCpuAsmOptimizer.OptPass1SXTW
|
2022-08-31 20:33:59 +02:00 |
|
florian
|
5a60eac0c8
|
+ MovzMovz2Movz optimization
|
2022-08-29 21:36:14 +02:00 |
|
florian
|
ceab50cafb
|
* use simpler FMOV instead of UMOV
|
2022-08-03 22:42:25 +02:00 |
|
J. Gareth "Curious Kit" Moreton
|
d6ff4ed967
|
* arm/a64: New sbfx/ubfx -> mov optimisation
|
2022-07-30 18:36:16 +00:00 |
|
J. Gareth "Curious Kit" Moreton
|
637645b6d6
|
* a64: New movz reg,#0 -> mov reg,xzr (or wzr) optimisation
|
2022-07-30 18:36:16 +00:00 |
|
Robert Roland
|
7cefe8a822
|
Adding AArch64 CurrentEL register
CurrentEL is used to determine the current "exception level" in the CPU.
It has four possible results:
0b00 - EL0 - Application
0b01 - EL1 - Rich OS
0b10 - EL2 - Hypervisor
0b11 - EL3 - Firmware
https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/CurrentEL--Current-Exception-Level
https://developer.arm.com/documentation/102412/0100/Privilege-and-Exception-levels
|
2022-07-25 19:05:00 +00:00 |
|
Robert Roland
|
a19add9c88
|
Add cntfrq_el0 and cntpct_el0 AArch64 registers
|
2022-07-05 20:40:27 +00:00 |
|
florian
|
81fd3e2748
|
* more readable fix for the missing ait_instruction check
|
2022-05-15 19:32:27 +02:00 |
|
J. Gareth "Curious Kit" Moreton
|
27db63969a
|
* a64: Fix where hp1's was assumed to be an instruction and not actually checked
|
2022-05-15 16:47:55 +00:00 |
|
florian
|
e8da1d081a
|
+ Aarch64: MovOp2AddUtxw optimization
|
2022-05-14 22:30:56 +02:00 |
|
Jonas Maebe
|
9813eb9048
|
AArch64 asm reader: add support for fpcmp(e) conditions
Resolves #39643
|
2022-04-03 13:40:21 +02:00 |
|
florian
|
27fb9086aa
|
* cleanup: cs_opt_loopunroll is a generic optimization for a long time already
|
2022-03-08 23:03:18 +01:00 |
|
Robert Roland
|
fbc65314b9
|
Correct linker script for aarch64-embedded
Start address was wrong, should be 0x80000, not 0x8000
|
2022-01-22 22:28:38 +01:00 |
|
florian
|
a362c93f73
|
* Aarch64: operations affect always the full 64 bit register, so
TCpuAsmOptimizer.RegLoadedWithNewValue can use SuperRegistersEq
|
2022-01-20 22:15:14 +01:00 |
|
Robert Roland
|
86c097086a
|
Additional copyright header
|
2022-01-05 12:29:00 +00:00 |
|
Robert Roland
|
53e5a4a03a
|
Adding aaarch64-embedded target
This adds support for aarch64-embedded, specifically for the Raspberry Pi 3.
Uses UART0 at 115200 baud 8N1 for console IO.
|
2022-01-05 12:29:00 +00:00 |
|
florian
|
e443936e12
|
+ in_min/max_dword/longint support for aarch64
|
2021-12-19 16:16:44 +01:00 |
|