Commit Graph

13 Commits

Author SHA1 Message Date
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references,
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
2016-11-27 18:17:37 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095
git-svn-id: branches/hlcgllvm@30101 -
2015-03-05 20:32:15 +00:00
sergei
3b06465322 + MIPS: support replacement spilling for mov.s, mov.d and (partially) mtc1 instructions.
git-svn-id: trunk@28530 -
2014-08-27 21:26:38 +00:00
Jonas Maebe
7949bebb8d * synchronised with r28168 of trunk
git-svn-id: branches/hlcgllvm@28169 -
2014-07-05 21:30:28 +00:00
sergei
25037f5318 - MIPS: completely removed trgcpu.add_constraints method.
While it can be correct from some point of view, it does not prevent aliasing a single-precision register into upper half of double-precision one. This is currently handled by making only even floating-point registers available to RA. At the same time, it somehow (possibly due to another bug in RA) generates a lot of unnecessary moves, as if physical double-precision registers conflict with each other. Anyway, removing it considerably improves the code without regressions in the test suite.

git-svn-id: trunk@27999 -
2014-06-19 03:59:24 +00:00
Jonas Maebe
5ef93e85b8 + added extra "orgsupreg" parameter to do_spill_read/do_spill_written/
do_spill_replace routines, will be necessary by llvm register
    allocator to determine the tdef corresponding to that register
  * replaced uses of taicpu with tai_cpu_abstract_sym in the register
    allocator so that it can work both with taicpu and taillvm instructions

git-svn-id: branches/hlcgllvm@26043 -
2013-11-11 11:15:43 +00:00
sergei
8b8553991a + MIPS: prevent coalescing written-to registers with $sp,$fp,$zero and $at.
+ Implemented subset of "spill replace" functionality, replacing moves from/to spilled registers with loads/stores to spill locations. This helps to reduce amount of instructions.

git-svn-id: trunk@24900 -
2013-06-15 04:04:08 +00:00
sergei
1421998752 * MIPS register spilling: relocations are not needed to load constant values, and offset limit is 32767, not 4095.
git-svn-id: trunk@23675 -
2013-02-28 20:43:38 +00:00
florian
de4a96f96d * fixes several register allocation related mips issues
* fixes range check error in mips code

git-svn-id: trunk@20266 -
2012-02-05 21:58:45 +00:00
florian
28036ed068 * fix some mips compiler issues, system unit compilation is getting forward
git-svn-id: trunk@20258 -
2012-02-04 22:53:52 +00:00
Jonas Maebe
f302fcdc98 + TSubRegisterSet definition forgotten to commit in r15952
* fixed compilation on non-x86 platforms after r15952

git-svn-id: trunk@15956 -
2010-09-09 08:48:02 +00:00
florian
e5ebb2a26e * started to integrate the code of David Zhang's MIPS code from fpc-mips on sf into fpc trunk
git-svn-id: trunk@14219 -
2009-11-19 22:07:10 +00:00