* generate code to load the TOC register if it's required, and
emit the the ".localentry" directive to indicate to the linker
where the actual function body starts
* support the ".localentry" directive in the ppc64 assembler reader
o disable the fpc_qword_to_double() assembler implementation for
ELFv2, because we can't manually insert the .localentry directive
before the stack allocation code
* perform indirect calls on ppc64 via R12 in ncgcal, as R12 needs to
contain the function address on entry on ppc64/ELFv2 (and it's
a volatile register, so there's no problem with always using
it)
git-svn-id: trunk@30198 -
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.
git-svn-id: trunk@26886 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
(avoids imaginary register number in "# Var I in register .." assembler comments.
* dbgdwarf.pas : Support register variables as register pairs.
Does not yet handle case of changing registers.
* symsym.pas : add currentregloc field to tabstractnormalvarsym class,
to be able to track changing registers used for a given variable.
* aasmtai.pas : Update currentregloc field of tai_varloc.create sym parameter.
* ncgutil.pas : Only generate a tai_varloc if the new registers are different for the variable.
git-svn-id: trunk@22508 -
and add usermode parsing of LDM/STM ops
This patch basically extends the ARM assembly reader a bit to properly parse CPSR and
SPSR flags for the MSR opcode, and allows the reader to understand
the ^ modifer for register lists for STMxx and LDMxx.
Previously the following combinations weren't possible in straight assembler:
MRS R0, CPSR
MRS R0, SPSR
MSR CPSR_CX, R0
LDMIA SP, {R0-R15}^
etc..
git-svn-id: trunk@22502 -
