Commit Graph

28 Commits

Author SHA1 Message Date
sergei
dc628b8969 * x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
git-svn-id: trunk@27934 -
2014-06-11 22:31:40 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler
git-svn-id: trunk@27214 -
2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke
git-svn-id: trunk@27200 -
2014-03-20 12:03:52 +00:00
florian
7028210817 + tzcnt assembler instruction
git-svn-id: trunk@26506 -
2014-01-18 12:11:50 +00:00
nickysn
f6e846c574 + added the NEC V20/V30 instructions
git-svn-id: trunk@25750 -
2013-10-11 21:27:56 +00:00
florian
9b6094a58c + added a few BMI instructions to see if they can be encoded
git-svn-id: trunk@24907 -
2013-06-16 09:35:21 +00:00
florian
283ff05127 * merged avx support in inline assembler developed by Torsten Grundke
git-svn-id: trunk@22568 -
2012-10-06 19:47:18 +00:00
florian
c011949765 + iretq for x86_64
git-svn-id: trunk@18273 -
2011-08-19 12:56:26 +00:00
sergei
0231863fce + Added missing PMULLD instruction, part of Mantis #19910
git-svn-id: trunk@18106 -
2011-08-06 06:59:33 +00:00
sergei
3b979fef6d * Re-commit r17437 after more testing and fixing aasmcpu.pp in r17449.
git-svn-id: trunk@17452 -
2011-05-14 11:04:52 +00:00
sergei
b257231203 * Revert r17437, it breaks builds with -O2 and builds on i386 (although -O- on x86_64 is ok).
git-svn-id: trunk@17439 -
2011-05-12 23:53:18 +00:00
sergei
1d81a1244b A big update of x86 instruction table, part 1 (mostly SIMD instructions):
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.

git-svn-id: trunk@17437 -
2011-05-12 19:49:19 +00:00
sergei
6739cec2b9 * Flagged with NOX86_64 instructions/encodings that are invalid in 64-bit mode.
* AESKEYGENASSIST is not ATT-specific name, it is used by Intel-style assemblers as well. Also updated tests/test/taes1.pp to reflect the change.
+ Added SCASQ, resolves #16730 (other opcodes mentioned in that report were added/fixed earlier)

git-svn-id: trunk@17431 -
2011-05-11 15:50:59 +00:00
florian
9279c6955e * support for SSSE3, SSE4,1, SSE4.2, AES instructions set by Emelyanov Roman, resolves #18527
+ test for aes support

git-svn-id: trunk@17256 -
2011-04-05 20:22:57 +00:00
Jonas Maebe
9273856e84 * disallow pusha*/popa* for x86_64 (mantis #14862)
* disallow pushfd/popfd for x86_64 (mantis #14862)
  * fixed assembling popfq with the internal assembler (it needs a rex.w
    prefisx, while pushfq doesn't)
  * changed the default opcode size of pushf/popf/pusha/popa in
    {$asmmode intel} from "native size" to 16 bit (compatible with Intel
    manuals and Kylix; in AT&T mode, the default size for those operations
    remains the native one)
  * changed pushf/popf in rtl/i386/* into pushfd/popfd because of the
    previous change

git-svn-id: trunk@15546 -
2010-07-10 16:22:46 +00:00
florian
0e96eda236 + some sse4 instructions supported, resolves #9046
git-svn-id: trunk@7613 -
2007-06-09 19:45:06 +00:00
florian
a19ed91cc3 * fix for jcxz, jecxz and jrcxz on 64 bit platforms
git-svn-id: trunk@6400 -
2007-02-10 21:05:27 +00:00
Jonas Maebe
c1df4454fe * cmpxchg8b doesn't have a size suffix
git-svn-id: trunk@6164 -
2007-01-24 15:15:04 +00:00
florian
5ece7cbc2f * first part of x86-64 assembler
git-svn-id: trunk@2824 -
2006-03-09 22:05:16 +00:00
daniel
45bcc5b07a * Add support for jmp $0011:$22334455 to Intel asm reader, request from
a user that is writing an operating system.
  * Fix mkx86ins bug to interpret imm16:imm32 as a single operand

git-svn-id: trunk@606 -
2005-07-10 07:42:14 +00:00
florian
ebcb69478f * fixed a lot of stuff for fpu/mm register variables
git-svn-id: trunk@199 -
2005-06-04 21:23:15 +00:00
peter
406eb57a59 * MOVSL fixed 2004-04-08 16:49:42 +00:00
peter
e6929a1a32 * more x86_64 parameter fixes
* tparalocation.lochigh is now used to indicate if registerhigh
    is used and what the type is
2004-02-09 22:14:17 +00:00
florian
dd2bb53aa5 + possible sse2 unit usage for double calculations
* some sse2 assembler issues fixed
2003-12-25 12:01:35 +00:00
florian
f495796796 * x86 instruction table updated to nasm 0.98.37:
- sse3 aka prescott support
      - small fixes
2003-09-09 12:54:45 +00:00
florian
59abf2555b * types.pas renamed to defbase.pas because D6 contains a types
unit so this would conflicts if D6 programms are compiled
  + Willamette/SSE2 instructions to assembler added
2002-07-20 11:57:52 +00:00
peter
a45e77c4a2 * move also the i386*.inc to i386/ 2000-10-15 09:41:37 +00:00