- RTL: removed MIPS,SPARC and m68k-specific implementations of Abs(longint), and marked the generic one as required for bootstrapping purposes only.
git-svn-id: trunk@27857 -
following cases:
1) external linking is already enabled
2) target does not support an internal linker
3) the 'omit linking stage' option is used
git-svn-id: trunk@27543 -
is 386+ only and the internal handling was not used anyway on i8086, due to
some nested defines in systemh.inc missing on i8086.
git-svn-id: trunk@26592 -
Although basic things work (no regressions in test suite, also with TEST_OPT=-O2), there are some secondary issues/TODOs:
- Exception frame around PASCALMAIN is not properly removed in DLLs
- No stack traces yet
- Stack overallocated in finalizer procedures, their entry/exit code needs cleanup
- Signals unit is probably completely broken.
git-svn-id: trunk@26225 -
default -O1/2/3 optimization levels and supported optimization switches
(e.g. -Ooregvar is not supported for the llvm target, nor needed)
git-svn-id: branches/hlcgllvm@26055 -
o no support yet for many ait_* types, although eventually most of them
shouldn't be generated at all for the llvm target
o no support yet for calling "opt" (which optimises llvm bitcode) before
calling llc (which translates llvm bitcode into native code) -- compile
with -s and manually call "opt" with -std-compile-opts, -O1, -O2 or -O3
if you want to experiment
o override the assembler writer with the llvm one when compiling an llvm-
targeting compiler
o override the assembler file extension with .ll when compiling an llvm-
targeting compiler
git-svn-id: branches/hlcgllvm@26054 -
target is now set before the second pass of parsing the command line
arguments. Then during the second pass, it can be overriden.
git-svn-id: trunk@25607 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
