m68k/cgcpu.pas, tcg68k:
+ overload "a_loadfpu_ref_cgpara" and use the 64-bit code generator to pass Doubles if they are located in references
Fixes around nearly 100 tests.
git-svn-id: trunk@23597 -
* initialize paraloc^.size to OS_INT instead of leaving it at 0
This fixes tests/test/cg/ttryexc1.pp. The problem was that the raise node generated code which resulted in a word(!) move of the raised object's address to the stack location for fpc_raiseexception. This then resulted in an error when freeing the exception object.
git-svn-id: trunk@23465 -
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
* add all Sxx instructions as "operand_write" instructions
m68k/n68kadd.pas, t68kaddnode.getresflags:
* use the correct operation in case of swapped nodes
m68k/cgcpu.pas, tcg68k.g_flags2reg:
- don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
- NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
* simplify the method by handling the address register case only when necessary
git-svn-id: trunk@23383 -
use the correct flag for the copy loop: we jump back to the copy code as long as the value is positive aka BPL instead of BMI
This fixes around 30 tests (it fixes a quite bit more, but now some other tests seem to be broken...)
git-svn-id: trunk@23373 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
+ a_op64_reg_reg: add support for "NEG" and "NOT" of 64-bit values
+ a_op64_const_reg: make sure that we know whether a NEG or NOT with a constant is performed
git-svn-id: trunk@22930 -
* in case of copying from the parameter location to the local location we need to use the alignment size for the source as byte/word values are passed as LongInts (this is how the ABI is specified)
git-svn-id: trunk@22924 -
+ add routine "call_rtl_moddiv_reg_reg" which handles the calling of "fpc_div_longint", "fpc_div_dword", "fpc_mod_longint" and "fpc_mod_dword"
* emit_mod_reg_reg & emit_div_reg_reg: use the new method instead of doing the call oneself
=> "Str(SomeInt, SomeStr)" and "Writeln(SomeInt)" now works
git-svn-id: trunk@22893 -
+ add methods "call_rtl_mul_const_reg" and "call_rtl_mul_reg_reg" which can call the RTL helpers "fpc_mul_longint" and "fpc_mul_longword" (based on AVR code)
* use the new call methods for the RTL to correctly pass the parameters (on the stack, not in registers...)
git-svn-id: trunk@22892 -
* don't do a sign_extend, but use the correct move size to copy the const; this fixes the setting of the line ending style inside of "Assign"
=> output of strings does now work correctly!
git-svn-id: trunk@22890 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
for "CMP" it is important to note that the first operand (which can be basically a register, a constant or a reference) is substracted from the second operand (which needs to be a data register) and not the other way round
git-svn-id: trunk@22798 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
fix the double running of second_pass in the way it was intended to work: check for left.expectloc instead of left.location.loc
git-svn-id: trunk@22788 -
