paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-05-15 10:02:54 +02:00
Code Issues Packages Projects Releases Wiki Activity
42,428 Commits 100 Branches 75 Tags 306 MiB
9c54cdc85d
Commit Graph

87 Commits

Author SHA1 Message Date
sergei
9c54cdc85d * x86: Cleaned out addr_far,addr_far_ref used to encode far calls/jumps. NASM (and FPC x86 assembler based on it) already have opsize=S_FAR for this purpose. 
git-svn-id: trunk@27037 -
 2014-03-08 22:54:43 +00:00
nickysn
b672bc754a - rm references to system_i386_darwin and system_i386_iphonesim from 
tcg8086.init_register_allocators

git-svn-id: trunk@26910 -
 2014-03-01 12:52:31 +00:00
nickysn
a31b7d485f * tcg8086.init_register_allocator: instantiate trgintcpu instead of trgcpu for 
the integer registers in all cases

git-svn-id: trunk@26909 -
 2014-03-01 12:50:26 +00:00
nickysn
fc29e10349 * allow the use of inc/dec when adding/subtracting 32 or 64-bit constants with 
the highest word equal to one and the lower parts zero

git-svn-id: trunk@26907 -
 2014-03-01 10:25:46 +00:00
sergei
9c1f917e3a * a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around. 
+ x86 targets now directly call procedure variables located in references.
- a_call_ref method removed from tcg and thlcgobj.

git-svn-id: trunk@26666 -
 2014-02-03 13:28:56 +00:00
nickysn
85dd9e5789 + added a size parameter to optimize_op_const and do a sign extension of the 'a' parameter up from the specified size, so that things like (i and $ffffffff) get optimized away the same way as (i and -1) 
git-svn-id: trunk@26561 -
 2014-01-22 15:00:34 +00:00
nickysn
529008e031 * emit MUL (when overflow checking is off), instead of IMUL for OP_IMUL in 
tcg8086.a_op_const_reg, when the target CPU is 8086/8088, because it's
  supposed to be faster on these processors, according to Intel's instruction
  timings.

git-svn-id: trunk@26493 -
 2014-01-17 21:23:42 +00:00
nickysn
767a0f1187 - rm TODO comment about the IMUL optimization with SHL from 
tcg8086.a_op_const_reg, since that optimization is already done in
  optimize_op_const, which is called earlier in the same method.

git-svn-id: trunk@26488 -
 2014-01-17 10:28:30 +00:00
nickysn
1a846e7c71 - rm TODO comment for overflow checking from tcg8086.a_op_const_reg, since 
overflow checking should not be implemented there. It should only leave the
  flags in place for the jo instruction, which the IMUL instruction already
  does.

git-svn-id: trunk@26487 -
 2014-01-17 10:26:20 +00:00
nickysn
b8203a3406 * fixed tcg8086.gen_cmp32_jmp1 for the less than/greater than cases 
git-svn-id: trunk@26370 -
 2014-01-03 18:06:21 +00:00
nickysn
cf6f408214 + implemented the tcg8086.a_cmp_*_*_label methods for i8086. How did the i8086 
code generator even work without these?

git-svn-id: trunk@26362 -
 2014-01-03 03:31:51 +00:00
nickysn
dcb9306de8 * perform the OP_AND, OP_OR and OP_XOR optimizations for 0 and $FFFF values 
independently also in tcg8086.a_op_const_ref

git-svn-id: trunk@26345 -
 2014-01-01 17:45:40 +00:00
nickysn
9a1e33d2a0 * tcg8086.a_op_const_reg: perform the OP_AND, OP_OR and OP_XOR optimizations for 
$0000 and $FFFF values on the low and the high words independently.

git-svn-id: trunk@26344 -
 2014-01-01 14:57:44 +00:00
nickysn
9eb4419ba3 * fixed the conversion and assignment to the 64-bit boolean types on the i8086 
git-svn-id: trunk@26343 -
 2013-12-31 17:18:20 +00:00
nickysn
974fea30b2 * use only one temporary 16-bit register, instead of two in tcg8086.g_flags2ref 
when the target ref is 32-bit.

git-svn-id: trunk@26342 -
 2013-12-31 16:27:11 +00:00
nickysn
bda163544a * tcg8086.g_flags2reg: restore the register back to the original size after the 
16-bit inc

git-svn-id: trunk@26337 -
 2013-12-31 13:15:30 +00:00
nickysn
fbd05c4e12 * Improved code generation in tcg8086.g_flags2reg for the case when target reg 
size is >=16-bit:
  o Generated code is now one instruction and one byte shorter.
  o No 8-bit subregisters are used, which reduces register pressure.

git-svn-id: trunk@26336 -
 2013-12-31 11:31:23 +00:00
nickysn
d57d982be7 * simpler handling of moves from a smaller to a larger cgsize in 
tcg8086.a_load_reg_ref, which additionally fixes the following issues:
  o The higher parts of the source register is no longer modified.
  o The source register's size is no longer modified with makeregsize.
  o Conversion from OS_S8 to a larger size is now supported.

git-svn-id: trunk@26335 -
 2013-12-31 00:33:37 +00:00
nickysn
5d0814016d * improvements and fixes in tcg8086.a_load_reg_reg and .a_load_ref_reg: 
o When expanding from a OS_8 to a 16-bit or 32-bit tcgsize, use the R_SUBH
    subregister to initialize the high 16 bits of the register to zero. This
    generates shorter and faster code, without increasing register
    interferences, because R_SUBH has the same register constraints on i8086 as
    R_SUBL, which is already used on the same imaginary register.
  o After performing operations on the 8-bit subparts of a register that was
    initially 16-bit, call makeregsize(OS_16) to notify the register allocator
    that the register is once again 16-bit.

git-svn-id: trunk@26328 -
 2013-12-30 21:20:10 +00:00
nickysn
6d48b32115 * fixes and improvements in tcg8086.a_load_reg_reg for the case when the src and 
dest are subregisters of the same superregister, but of different sizes:
   o Do not emit spurious moves from a register to the same register.
   o Correctly support the case when converting from 16-bit to 32-bit int.
     Previously it didn't work correctly, because in this particular case, due
     to the way the GetNextReg scheme works, we have reg1=reg2.

git-svn-id: trunk@26313 -
 2013-12-29 17:15:58 +00:00
nickysn
fdd36b4603 * on i8086 with regvars on, do not notify the register allocator of moves to BX. 
This fixes compilation of unit math (and the whole RTL) with regvars enabled.

git-svn-id: trunk@26282 -
 2013-12-25 12:19:21 +00:00
nickysn
8bfe2a56dd * optimized SAR by 31 to use only one SAR instruction in tcg8086.a_op_const_reg 
git-svn-id: trunk@25883 -
 2013-10-30 16:53:59 +00:00
nickysn
bfd31e7516 * optimizations in tcg8086.g_copyvaluepara_openarray: 
- when elesize=2, avoid the SHR CX,1 instruction
  - use rep movsw even for odd elesizes, unless cs_opt_size is set

git-svn-id: trunk@25829 -
 2013-10-19 15:07:55 +00:00
nickysn
ff9ce0d20d * tcg8086.g_copyvaluepara_openarray improvements: 
- use a_op_const_reg for the multiplication, instead of emitting directly
    instructions, which are 186+
  - avoid using IMUL twice, when the element size is not power of two
  - rm the system_i386_win32 leftovers

git-svn-id: trunk@25826 -
 2013-10-18 22:35:51 +00:00
nickysn
ef51c8c5a2 * fixed the interface wrapper code generation for virtual methods on i8086 in 
the medium memory model

git-svn-id: trunk@25817 -
 2013-10-18 12:11:50 +00:00
nickysn
116d3746ca * fixed the stack offset to the self parameter when generating an interface 
wrapper for a virtual method in tcg8086.g_intf_wrapper

git-svn-id: trunk@25816 -
 2013-10-18 10:56:04 +00:00
nickysn
83aa50de74 * emit a far jmp in the interface wrapper on i8086 in far code memory models 
git-svn-id: trunk@25812 -
 2013-10-17 21:55:45 +00:00
nickysn
814e1297ed * tcg8086.g_adjust_self_value fixed for far code memory models 
git-svn-id: trunk@25798 -
 2013-10-15 23:34:18 +00:00
nickysn
0aff18ac61 + implemented tcg64f8086.a_op64_ref_reg 
git-svn-id: trunk@25707 -
 2013-10-07 00:17:03 +00:00
nickysn
3cdbf9a805 + implemented tcg64f8086.a_op64_const_ref 
git-svn-id: trunk@25706 -
 2013-10-06 23:56:25 +00:00
nickysn
3bdd3d9a4e + optimization in tcg64f8086.a_op64_const_reg for OP_ADD and OP_SUB when the 
lowest 48, 32 or 16 bits of the constant are zeros

git-svn-id: trunk@25705 -
 2013-10-06 23:43:38 +00:00
nickysn
88c7ca96c5 + optimization in tcg8086.a_op_const_reg and .a_op_const_ref for 32-bit OP_ADD 
and OP_SUB when the low 16 bits of the const are 0

git-svn-id: trunk@25704 -
 2013-10-06 23:23:06 +00:00
nickysn
8f44e729cc * tcg8086.a_op_const_ref and .a_op_const_reg: when splitting a 32-bit OP_AND, 
OP_OR or OP_XOR operation into two 16-bit parts, call a_op_const_reg/ref
  recursively for the 16-bit parts, so certain optimizations can be done if the
  low or high 16-bit of the const are $ffff.

git-svn-id: trunk@25703 -
 2013-10-06 23:02:07 +00:00
nickysn
bd0585274e * tsettings.enablecld converted to a targetswitch ts_cld 
git-svn-id: trunk@25592 -
 2013-09-28 13:41:58 +00:00
nickysn
52fcc0a407 + added a new x86-specific compiler option 'enablecld', which controls whether 
the compiler should emit a CLD before using the x86 string instructions.

git-svn-id: trunk@25590 -
 2013-09-28 11:54:02 +00:00
nickysn
1f783f539c * emit a cld instruction before the rep movsXX in tcg8086.g_copyvaluepara_openarray as well 
git-svn-id: trunk@25556 -
 2013-09-24 20:09:11 +00:00
florian
11ff8a4ec1 + support register parameters with multiple locations 
git-svn-id: trunk@25238 -
 2013-08-11 16:12:39 +00:00
florian
57d4185d44 * allocate/deallocate cpu registers as late/early as possible, this gives the reg. allocator more flexibility 
git-svn-id: trunk@25229 -
 2013-08-08 20:55:45 +00:00
sergei
a21a20d559 + i8086-specific version of g_stackpointer_alloc. 
git-svn-id: trunk@25219 -
 2013-08-06 08:11:39 +00:00
nickysn
b81f0ab50d + implemented tcg8086.a_call_reg_far; very hacky, but still better than doing a near call, when it should be far 
git-svn-id: trunk@24856 -
 2013-06-09 22:16:40 +00:00
nickysn
604b7c9deb + added cg.a_call_ref_near and a_call_ref_far 
git-svn-id: trunk@24853 -
 2013-06-09 20:22:47 +00:00
nickysn
af54de6d56 + added tcg8086.a_call_name_far and .a_call_name_static_far; a_call_name and a_call_name_static overriden and call near or far depending on the memory model 
git-svn-id: trunk@24828 -
 2013-06-09 10:54:30 +00:00
nickysn
aa63efc27e * emit a far ret instruction in the exit code of far procedures 
git-svn-id: trunk@24817 -
 2013-06-08 20:40:50 +00:00
nickysn
e2241d97a2 * i8086 optimizations for 32-bit OP_SAR with const >= 16 
git-svn-id: trunk@24757 -
 2013-06-02 09:35:30 +00:00
nickysn
55a071692e * i8086 optimizations in op_const_reg for 32-bit OP_SHL and OP_SHR with const >= 16 
git-svn-id: trunk@24756 -
 2013-06-02 08:58:50 +00:00
nickysn
ec76b2cf40 * refactored the segment-in-integer-register reference support, so it's handled in make_simple_ref, instead of all over the place in the code generator 
git-svn-id: trunk@24752 -
 2013-06-01 22:18:09 +00:00
nickysn
e243b6b869 * never use the 66h prefix when pushing/popping segment registers on i8086, as the stack is aligned on 2 bytes there 
git-svn-id: trunk@24729 -
 2013-06-01 16:03:14 +00:00
nickysn
c2e3fb5918 + emit proper interrupt procedure entry/exit code on i8086 
git-svn-id: trunk@24728 -
 2013-06-01 15:50:11 +00:00
nickysn
c271594b4f + optimized implementation of 32-bit OP_SHL,OP_SHR and OP_SAR in tcg8086.a_op_const_reg 
git-svn-id: trunk@24660 -
 2013-05-31 11:03:36 +00:00
nickysn
06838be452 * fixed bug when passing a 'single' floating point type parameter via tcg8086.a_load_ref_cgpara 
git-svn-id: trunk@24592 -
 2013-05-25 13:37:24 +00:00