using it in inline asm causes an internal error and removing it didn't show
any regressions after running the testsuite on i386-linux.
git-svn-id: trunk@25827 -
* Don't generate rex.w for "CALL|JMP|LCALL|LJMP regmem", they are 64-bit by default.
* LCALL,LJMP flagged as calljump instructions.
* LCALL,LJMP encode only far jumps and don't accept register operands.
* GAS writer: fixed writing rip-relative operands of calljump instructions.
+ test.
git-svn-id: trunk@19413 -
* Adjust rip-relative offsets using values known from calcsize, instead of reinterpreting the tail of instruction. This is simpler and remains the same regardless of particular codes used in opcode table.
* Reduced maxinfolen to 8.
- 'jmp imm64' and 64-bit versions of 'in' do not exist, removed.
git-svn-id: trunk@17546 -
* mkx86ins.pp: 'regmem' operand type in x86ins.dat must be converted to OT_RM_GPR, not OT_REGMEM. The latter does not restrict register type, allowing to use e.g. xmm registers in place of regular ones.
* Finished 'movd' and 'movq', added some tests for them to tasm2.pp.
git-svn-id: trunk@17515 -
* Optimized the opcode representation of movq and remaining 3DNow instructions
* Disallow immediates not fitting in 32 bits (Mantis #14685) + test
* Disallow push/pop with 32-bit operands in x86_64 + test
git-svn-id: trunk@17490 -
- Removed remaining address-size control codes \300 and \301
- Also removed codes \323, they are no longer necessary once REX is being written on the first literal.
git-svn-id: trunk@17457 -
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.
git-svn-id: trunk@17437 -
* Simplified REX handling: instead of useless adjusting instruction length on every REX change, adjust it just once, based on the final REX value.
* Similar for omitting REX.W in certain instructions: set a flag and consider it once the entire instruction has been processed. This removes the requirement for \335 to be the last opcode.
* maybewriterex also after $F2 prefix
* Fixed behavior of codes \310 and \311 (16- and 32-bit address respectively), this is needed for a few fancy instructions like LOOP and JCXZ, which honor address-size prefix instead of REX.
+ control code \361 for $66 prefix
+ IF_SSSE3, IF_SSE41, IF_SSE42 instruction flags (with dummy values)
x86/x86ins.dat:
* replaced literal $67 prefixes with \310 or \311
* marked encodings containing code \310 as NOX86_64
* replaced literal $48 prefixes with \326
git-svn-id: trunk@17433 -
* AESKEYGENASSIST is not ATT-specific name, it is used by Intel-style assemblers as well. Also updated tests/test/taes1.pp to reflect the change.
+ Added SCASQ, resolves#16730 (other opcodes mentioned in that report were added/fixed earlier)
git-svn-id: trunk@17431 -
* x86ins.dat: replaced codes \17 with literal zeros. They aren't necessary for FPC, and they were removed from NASM quite a while ago.
git-svn-id: trunk@17430 -
+ Added new value TAttSuffix.attsufINTdual, assigned it to movsX and movzX instructions
* Moved suffix-to-size translation tables from rax86att.pas to itcpugas.pas
+ Added x86_64 specific suffix-to-size translation, enabling BQ and WQ suffixes (LQ seems unnecessary at the moment)
* Fixed logic of tx86attreader.is_asmopcode so it only assigns dual suffix to instructions that explicitly allow it. This disambiguates cases like movsbq=movs+bq vs. cmovbq=cmovb+q
* As a net result: movz[bw]q and movs[bw]q now compile for x86_64; cmovbw and cmovbl which were incorrectly handled for i386 are now fixed.
+ Test for correct assembling of cmov.
git-svn-id: trunk@17353 -
* disallow pushfd/popfd for x86_64 (mantis #14862)
* fixed assembling popfq with the internal assembler (it needs a rex.w
prefisx, while pushfq doesn't)
* changed the default opcode size of pushf/popf/pusha/popa in
{$asmmode intel} from "native size" to 16 bit (compatible with Intel
manuals and Kylix; in AT&T mode, the default size for those operations
remains the native one)
* changed pushf/popf in rtl/i386/* into pushfd/popfd because of the
previous change
git-svn-id: trunk@15546 -
