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94 Commits

Author SHA1 Message Date
masta
c3a91c5022 Remove the postfix check in MovStrMov peephole optimizer for ARM 
We don't need to check for the postfix, PF_NONE/PF_H/PF_B are all ok for us and
can be intermixed. This allows the peephole optimizer to work for
strb and strh instructions.

git-svn-id: trunk@22367 -
 2012-09-10 14:57:43 +00:00
florian
03bf93488b * workaround for broken in operator 
git-svn-id: trunk@22329 -
 2012-09-05 15:00:04 +00:00
florian
de34eab23d + optimize and ...,255/strb ... sequence if possible 
git-svn-id: trunk@22323 -
 2012-09-05 11:24:03 +00:00
florian
93d0033282 * improve AndAnd2And optimization by checking if the first destination register is allocated after the second and 
git-svn-id: trunk@22322 -
 2012-09-05 11:23:05 +00:00
florian
8a6c65b008 * fix r22319: hp1 must have the same condition as p 
git-svn-id: trunk@22321 -
 2012-09-05 09:05:26 +00:00
florian
2f1989c1a6 * hp1 can have any condition in this case so don't access hp1.condition because it 
is not guranteed that hp1 is actually a tai_instruction before calling MatchInstruction

git-svn-id: trunk@22319 -
 2012-09-04 18:58:28 +00:00
masta
d8af83d252 Introduce a version of MatchInstruction for multiple instructions 
It is the same as the normal MatchInstruction function but supports to
be called with a set of TAsmOps instead of a single op.

git-svn-id: trunk@22231 -
 2012-08-24 15:54:36 +00:00
florian
6b73bc45c5 * check constant for being a valid offset 
git-svn-id: trunk@22230 -
 2012-08-24 09:16:47 +00:00
florian
58a85e79ce * set index register correctly * index register might not be changed 
git-svn-id: trunk@22229 -
 2012-08-24 09:16:38 +00:00
florian
245d8286d5 + LookForPostindexedPattern 
git-svn-id: trunk@22228 -
 2012-08-24 09:16:26 +00:00
masta
012da673a8 Use MatchInstruction in OpCmp2OpS 
MatchInstruction keeps the code a bit more readable and compact.

git-svn-id: trunk@22226 -
 2012-08-23 23:08:26 +00:00
florian
a016bc5ced * white space change 
git-svn-id: trunk@22224 -
 2012-08-23 21:04:31 +00:00
florian
f2ccd6e400 * when doing the AddSubLdr2Ldr optimization check also if the source register of the add is modified before the load 
git-svn-id: trunk@22223 -
 2012-08-23 21:04:21 +00:00
florian
4e2de05667 * don't apply the AddSubLdr2Ldr optimization if the base register in the reference is used/modified during the ldr/str 
git-svn-id: trunk@22222 -
 2012-08-23 21:04:11 +00:00
florian
d89b742109 * apply Add/SubLdr2Ldr only if no condition flags are involved 
git-svn-id: trunk@22221 -
 2012-08-23 21:04:02 +00:00
florian
73d540e7b5 * unsigned byte ldr/str allow also an offset of max. +/-4095 
git-svn-id: trunk@22220 -
 2012-08-23 21:03:52 +00:00
florian
9d20a73986 * optimize also str/ldrb/h/d 
git-svn-id: trunk@22219 -
 2012-08-23 21:03:44 +00:00
florian
1b3e03d72d + DEBUG_AOPTCPU to turn off peephole optimizer messages 
git-svn-id: trunk@22218 -
 2012-08-23 21:03:34 +00:00
florian
8a20ccc5f9 + Add/SubLdr2Ldr optimization 
git-svn-id: trunk@22217 -
 2012-08-23 21:03:24 +00:00
masta
b9fa9da629 Small fixes to OpCmp2OpS 
1.) For UMULL and UMLAL support we would have to make sure the following
code checks RdHi and RdLo, which is currently not supported.
The former code would transform the following

  umull r0, r1, r2, r3
  cmp   r0, #0
  bne   .LSomething

into

  umulls r0,r1,r2,r3
  bne    .LSomething

which is wrong. UMULL has a 64bit result in r1+r0 and checks the full 64bit for 0
before setting the Z flag.

2.) Support MLA.

3.) Support MI/PL/NE/EQ for all instructions. As all of them are setting
the N and Z flags in the same way only based on the result of the
operation not on its input values.

N:=Result[31];
Z:=Result = 0;

Wurst

git-svn-id: trunk@22213 -
 2012-08-23 14:22:29 +00:00
florian
3ad32b6e4e * opcode spelling fixed 
git-svn-id: trunk@22204 -
 2012-08-23 08:55:07 +00:00
florian
935985d0c0 * checked and updated valid opcode for OpCmp2OpS optimization 
git-svn-id: trunk@22203 -
 2012-08-23 08:55:03 +00:00
florian
70009e8ed1 * move flag allocation item 
git-svn-id: trunk@22202 -
 2012-08-23 08:54:58 +00:00
florian
2d2c66467c + optimize op ... / cmp .... when possible 
git-svn-id: trunk@22200 -
 2012-08-23 08:54:47 +00:00
florian
a92ca7c456 * adjust the reg. allocations of the target register in RemoveSuperfluousMove 
git-svn-id: trunk@22194 -
 2012-08-22 19:52:37 +00:00
florian
3d7b603d11 * get rid or move the allocation of the replaced register if possible 
git-svn-id: trunk@22193 -
 2012-08-22 19:52:30 +00:00
florian
77e579f59f * RemoveSuperfluousMove uses FindRegDeAlloc to find out if the register used in the move can be removed 
* RemoveSuperfluousMove fixes partially the register allocation changes caused by the mov

git-svn-id: trunk@22192 -
 2012-08-22 19:52:23 +00:00
florian
5fd457e586 * when determining of a register is used after an instruction, new allocs should not be taken into account 
git-svn-id: trunk@22189 -
 2012-08-22 19:52:03 +00:00
florian
c0425c48fd * make use of GetNextInstructionUsingReg 
git-svn-id: trunk@22186 -
 2012-08-22 19:51:40 +00:00
florian
f3f5be2af1 * RemoveSuperfluousMove should not mess with moves targetting lr or pc 
git-svn-id: trunk@22185 -
 2012-08-22 19:51:31 +00:00
florian
93eb20d407 + GetNextInstructionUsingReg 
git-svn-id: trunk@22184 -
 2012-08-22 19:51:19 +00:00
florian
2a14394cf5 * cleaned up scheduler code, created own scheduler class to avoid unneeded passes through the assembler 
git-svn-id: trunk@22133 -
 2012-08-19 19:15:34 +00:00
florian
a3bf956c33 * improved main loop of TCpuPreRegallocScheduler.PeepHoleOptPass1Cpu 
* reordered conditions in scheduler main loop so they abort potentially quicker

git-svn-id: trunk@22132 -
 2012-08-19 19:13:49 +00:00
florian
54e2b40ab4 * revert the parameter type change of the last commit, it was an overleft from a failed fix attempt 
git-svn-id: trunk@22116 -
 2012-08-17 19:36:37 +00:00
florian
45eafd3e65 * fix MovMov optimization if the second mov is a mov rX,rX 
git-svn-id: trunk@22114 -
 2012-08-17 19:36:22 +00:00
florian
4b4e08c28b * fixes copy&paste errors when moving end of live pointers 
git-svn-id: trunk@22113 -
 2012-08-17 19:36:16 +00:00
florian
53a0d3e3a3 * fixed typo when checking live start of references 
git-svn-id: trunk@22112 -
 2012-08-17 19:36:10 +00:00
florian
a693fe9fb7 + implemented TCpuPreRegallocScheduler.SwapRegLive and make use of it to be able to reschedule instructions before register allocation 
git-svn-id: trunk@22110 -
 2012-08-17 19:35:59 +00:00
florian
354cac2bb6 + completed arm architectures 
* ldrd/strd and pld collected under the edsp define

git-svn-id: trunk@22104 -
 2012-08-17 10:37:27 +00:00
florian
7588896775 * make use of cpuflags in the arm compiler 
* armv5te architecture

git-svn-id: trunk@22103 -
 2012-08-17 10:37:17 +00:00
florian
371ef7bada * cover more cases in AlignedToQWord 
git-svn-id: trunk@22060 -
 2012-08-11 15:11:43 +00:00
florian
db7e029574 * strd/ldrd optimization might be only done on dword operations 
git-svn-id: trunk@22059 -
 2012-08-11 15:11:10 +00:00
florian
8c45a909be + support ldr/ldr -> ldrd and str/str -> strd optimization where appliable 
git-svn-id: trunk@22058 -
 2012-08-11 11:45:54 +00:00
masta
9e039936bf Support more operators in FoldShiftProcess on ARM 
Now we can also fold shifts into teq, tst, cmp, cmn instructions.

git-svn-id: trunk@22023 -
 2012-08-07 06:46:32 +00:00
florian
023d632f44 * optimize also lsr/asr, lsl, lsr/asr sequences on arm 
git-svn-id: trunk@21981 -
 2012-07-28 22:30:11 +00:00
florian
c8435b503f * better folding of consecutive shift operations 
git-svn-id: trunk@21978 -
 2012-07-28 17:59:45 +00:00
masta
be6bf6e3f7 Fix possible access violation introduces in r21885 
r21885 added a new peephole optimizer. The associated code refactoring
missed a check for

  tai(hp1).typ = tai_instruction

Which can lead to an access violation later on, because the rest of the
code expects to find a taicpu in hp1.

git-svn-id: trunk@21949 -
 2012-07-22 18:06:08 +00:00
florian
701a5d76bb * remove unneeded movs 
git-svn-id: trunk@21885 -
 2012-07-11 20:58:52 +00:00
masta
5498456269 Add LsrAndLsr Peephole Optimizer for ARM 
Remove the superfluous and in:
mov r0, r0, lsr #24
and r0, r0, #255

Doing this allows for better shift-folding later

git-svn-id: trunk@21659 -
 2012-06-20 12:39:19 +00:00
florian
64ac48c815 * patch by Nico Erfurth: Better support for PLD on ARM 
git-svn-id: trunk@21572 -
 2012-06-09 17:28:05 +00:00