Rika Ichinose
900b1fc4ec
Check for refcount = 1 first.
2025-02-16 15:17:48 +03:00
florian
27e17e3186
+ RiscV64: make use of rev8 instruction
2025-02-13 22:44:44 +01:00
Rika Ichinose
840df7e243
Disable MemPos on JVM.
2025-02-10 19:22:41 +00:00
Rika Ichinose
c3f80014b4
Remove FDestroyCount.
2025-02-10 18:53:26 +00:00
Rika Ichinose
1e041077cc
Interface unref should zero the pointer first.
2025-02-09 15:25:33 +00:00
Rika Ichinose
98a5072fbe
Remove NewAnsiString & NewUnicodeString.
2025-02-09 14:27:09 +00:00
Rika Ichinose
f7f8c9a615
Publish System.MemPos.
2025-02-09 03:40:40 +03:00
Rika Ichinose
66d7408b3d
Faster Pos(ansistring).
2025-02-08 11:04:22 +00:00
Rika Ichinose
6631f83ccf
Change CompareChar uses inside compiler/RTL to CompareByte.
2025-02-07 20:51:50 +03:00
Michaël Van Canneyt
0b3d059458
* Allow host environmentto get main and self thread IDs. Needed for inter-thread messaging in browser
2025-02-07 16:42:44 +01:00
Rika Ichinose
6ccad3dc4e
Shortcut declocked on refcount = 1.
2025-01-31 22:03:25 +00:00
florian
212b0fb7a8
* cleanup
2025-01-30 22:49:29 +01:00
florian
cd76562339
+ atomic operations for RV32
2025-01-26 14:17:39 +01:00
florian
f8c09568d8
* RiscV: unify stack related functions
2025-01-25 23:20:11 +01:00
florian
c6a68abfb6
* RiscV: unify memory barrier functions
2025-01-25 15:00:40 +01:00
florian
ca53c5e7d4
* unify SysInitFPU and SysResetFPU on RiscV
2025-01-25 14:43:10 +01:00
Nikolay Nikolov
5e813e62f2
+ added function fpc_wasm_invoke_helper to the WebAssembly RTL
2025-01-25 08:21:56 +02:00
florian
28a9a44894
* call SysResetFPU and SysInitFPU in InitThread for the time being
2025-01-24 22:56:46 +01:00
Michaël Van Canneyt
28fc3da2bd
* Patch from Eric Grange to fix TRectF.FitInto
2025-01-24 11:53:09 +01:00
Pierre Muller
d2f5bbac50
Riscv64 linux also needs _STAT_VER_LINUX to be zero for correct libc rtl behavior
2025-01-23 22:38:07 +00:00
florian
9cac8e6183
+ add an SysInitFPU implementation
2025-01-23 23:00:30 +01:00
Pierre Muller
d959e47c83
Fix _FPC_xtensa_exit first parameter passing
2025-01-23 15:52:11 +00:00
Michaël Van Canneyt
925091d0d1
* Fix compilation when using threading
2025-01-23 14:48:57 +01:00
florian
02b31542f6
* make rounding mode and exception mask thread variables as well
2025-01-21 22:53:28 +01:00
Pierre Muller
7e5d9680c2
Fix compilation of riscvXX-linux targets with -dFPC_USE_LIBC
2025-01-20 22:48:39 +01:00
florian
b1c2023af1
+ support for RiscV hwprobe syscall
...
+ test
2025-01-19 18:42:04 +01:00
florian
a4ca9f5357
* upated syscalls
...
+ RiscV specific syscalls added
2025-01-18 23:04:07 +01:00
Pierre Muller
b1a47a5d7d
Use '__global_pointer$' special linker symbol to set gp,
...
because its value can be different from __BSS_END__ - 0x800.
Details from binutils-2.40/ld/emulparams/elf32lriscv-defs.sh
// We must cover as much of sdata as possible if it exists. If sdata+bss is
// smaller than 0x1000 then we should start from bss end to cover as much of
// the program as possible. But we can't allow gp to cover any of rodata, as
// the address of variables in rodata may change during relaxation, so we start
// from data in that case.
OTHER_END_SYMBOLS="${CREATE_SHLIB-__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));}"
2025-01-16 17:20:14 +00:00
Sven/Sarah Barth
9fccadc1f0
* leave GetFileContents() early if the file size is 0 to avoid a range error if the RTL is compiled with range checks
2025-01-13 23:30:02 +01:00
Sven/Sarah Barth
5af16b3da3
* apply patch by Michael Ring to fix compilation for ARM THUMB
2025-01-09 07:39:18 +01:00
Sven/Sarah Barth
f29fe358ad
- remove unnecessary defines
2025-01-08 23:06:29 +01:00
Sven/Sarah Barth
40725146cc
+ add intrinsic for 8-bit atomic cmpxchg for wasm32 (this way the fallback for cmxchg is no longer used for wasm32)
2025-01-08 23:06:29 +01:00
Michaël Van Canneyt
8488c87b20
* New fix for fpc_atomic_cmp_xchg_alu, as suggested by Sven
2025-01-08 14:56:16 +01:00
Michaël Van Canneyt
5d100fd2c6
cpuNbitalu is not the correct type for fpc_atomic_cmp_xchg_alu on webassembly
2025-01-08 12:06:52 +01:00
Michaël Van Canneyt
3f0593b554
* Better fix for atomic operations on wasm
2025-01-07 14:42:21 +01:00
Michaël Van Canneyt
ec7e917b1a
Use correct defines for ALUSInt, fixes problems encountered in webassembly
2025-01-06 14:10:27 +01:00
Rika Ichinose
9dfbc38a50
Don’t use explicit Move in Extract<T> and Swap<T>.
2024-12-23 21:06:22 +00:00
Rika Ichinose
f1050aeb73
Simplify dynarr.inc.
2024-12-22 21:41:31 +00:00
Michaël Van Canneyt
a8345da53f
* TBasicActionLink.Update must always return value. Fix issue #41070
2024-12-20 12:28:20 +01:00
Rika Ichinose
6035058a21
Shorten generic atomic implementations to offset the LoC cost of the commit before last.
...
This also fixes wrong fpc_atomic_sub_8 and fpc_atomic_sub_16 emulations.
2024-12-19 19:42:25 +00:00
Rika Ichinose
94a1f33f60
Shorten i386 and x86-64 atomic implementations to offset the LoC cost of the previous commit.
2024-12-19 19:42:25 +00:00
Rika Ichinose
bb43afd26d
Add more specialized atomics for i386 and x86-64.
2024-12-19 19:42:25 +00:00
Michaël Van Canneyt
73287c1fa8
* Patch from Bart B to improve Slice(). Fixes issue #41068
2024-12-18 20:41:55 +01:00
Sven/Sarah Barth
ae938e16a5
* correctly disable the Atomic*Lock functions for the fpc_atomic_cmp_xchg_*() helper fallback of the CPU size
2024-12-16 23:13:36 +01:00
Karoly Balogh
c2ceb4bb99
m68k-amiga: fix typo from commit e94d02a0 that broke the build
2024-12-13 01:18:31 +01:00
Sven/Sarah Barth
e94d02a067
* with all existing RTLs switched over to the atomic intrinsics, the define FPC_SYSTEM_INTERLOCKED_USE_INTRIN can be removed again
2024-12-12 22:05:20 +01:00
Sven/Sarah Barth
9b302983b0
* switch LoongArch 64 RTL to provide atomic intrinsic helpers instead of Interlocked* functions
2024-12-12 22:05:19 +01:00
Sven/Sarah Barth
16f9ab3bdb
* switch Xtensa RTL to provide atomic intrinsic helpers instead of Interlocked* functions
2024-12-12 22:05:19 +01:00
Sven/Sarah Barth
128a87a2dc
* switch AVR RTL to provide atomic intrinsic helpers instead of Interlocked* functions
2024-12-12 22:05:18 +01:00
Sven/Sarah Barth
19d908a964
* switch RISC-V 64 RTL to provide atomic intrinsic helpers instead of Interlocked* functions
2024-12-12 22:05:18 +01:00
