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eb26cd55d4
Commit Graph

118 Commits

Author SHA1 Message Date
nickysn
eb26cd55d4 + implemented OP_XOR in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44661 -
 2020-04-09 14:29:56 +00:00
nickysn
7a86d193cc + implemented OP_OR in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44660 -
 2020-04-09 14:24:36 +00:00
nickysn
f00f39abef + implemented OP_AND in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44659 -
 2020-04-09 14:21:57 +00:00
nickysn
5360770ed2 + implemented OP_SUB in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44658 -
 2020-04-09 13:41:28 +00:00
nickysn
75a2f0352e * fixed 64-bit OP_ADD in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44657 -
 2020-04-09 13:28:22 +00:00
nickysn
a419018ff0 + handle fromsize>tosize in tcgz80.a_load_reg_reg 
git-svn-id: branches/z80@44656 -
 2020-04-09 13:23:10 +00:00
nickysn
ce56125e40 + implemented OP_ADD in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44655 -
 2020-04-09 13:16:48 +00:00
nickysn
62cc60d081 * use register L for returning 8-bit values, DEHL for 32-bit values (SDCC-compatible) 
git-svn-id: branches/z80@44654 -
 2020-04-09 00:11:39 +00:00
nickysn
3c8ed1cfbc * use 8-bit registers for the function return regs 
git-svn-id: branches/z80@44653 -
 2020-04-09 00:07:20 +00:00
nickysn
b896d2fea2 + implemented sign extension in tcgz80.a_load_reg_ref 
git-svn-id: branches/z80@44652 -
 2020-04-08 23:59:58 +00:00
nickysn
6fea99ac9d + implemented sign extension in tcgz80.a_load_ref_reg 
git-svn-id: branches/z80@44651 -
 2020-04-08 23:57:26 +00:00
nickysn
df59c070a1 + implemented sign extension in tcgz80.a_load_reg_reg 
git-svn-id: branches/z80@44650 -
 2020-04-08 23:50:14 +00:00
nickysn
b84bcdaeee + implemented unsigned int extension in tcgz80.a_load_ref_reg 
git-svn-id: branches/z80@44648 -
 2020-04-08 22:30:35 +00:00
nickysn
d0166242b3 + support unsigned sign extension in tcgz80.a_load_reg_reg 
git-svn-id: branches/z80@44646 -
 2020-04-08 20:23:16 +00:00
nickysn
7d9658e2ba + support unsigned expansion in tcgz80.a_load_reg_ref 
git-svn-id: branches/z80@44645 -
 2020-04-08 20:12:17 +00:00
nickysn
5e94fbff54 + added method make_simple_ref (empty for now, but will be implemented later) 
git-svn-id: branches/z80@44640 -
 2020-04-07 23:12:33 +00:00
nickysn
7fd807905f + initial implementation of pushing ref params in tcgz80.a_load_ref_cgpara 
git-svn-id: branches/z80@44639 -
 2020-04-07 22:55:33 +00:00
nickysn
c53cd30e7f + implemented tcgz80.a_load_reg_cgpara for pushing 1-byte parameters on the stack 
git-svn-id: branches/z80@44638 -
 2020-04-07 22:34:05 +00:00
nickysn
4fc83a44d3 + implemented byte-sized inc/dec by 1 in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44631 -
 2020-04-07 01:03:02 +00:00
nickysn
0d04d198fe + emit warnings for unimplemented ops in tcgz80.a_op_const_reg_internal 
git-svn-id: branches/z80@44630 -
 2020-04-07 00:55:54 +00:00
nickysn
b2549b63cd * implemented pop_parasize for the Z80 and declared stdcall to be a clearstack pocall on this arch 
git-svn-id: branches/z80@44629 -
 2020-04-07 00:07:34 +00:00
nickysn
472ac716b7 * mark the 8-bit versions of the registers as volatile when calling procedures/functions 
git-svn-id: branches/z80@44628 -
 2020-04-06 23:31:20 +00:00
nickysn
f15b54085c * fixed tcgz80.a_load_const_cgpara for pushing params on the stack 
git-svn-id: branches/z80@44627 -
 2020-04-06 23:15:00 +00:00
nickysn
fe20a00711 * don't typecast the const to aint in taicpu.op_const_reg and .op_reg_const, because, on the Z80, aint 
is 8-bit (we treat it as having an 8-bit ALU), but it also has 16-bit instructions and registers,
  that can take 16-bit consts

git-svn-id: branches/z80@44626 -
 2020-04-06 23:12:02 +00:00
nickysn
3e3a392d88 * z80 regdat files regenerated 
git-svn-id: branches/z80@44625 -
 2020-04-06 22:49:05 +00:00
nickysn
d8ca077c33 + add externals as .globl directives in the sdcc-sdasz80 assembler output 
git-svn-id: branches/z80@44587 -
 2020-04-04 23:15:57 +00:00
nickysn
c0b4e5c994 - removed the unused 's: topsize' parameter to TSdccSdasZ80Assembler.WriteOper 
git-svn-id: branches/z80@44586 -
 2020-04-04 23:04:35 +00:00
nickysn
1b06b649a7 * use is_calljmp to determine whether to use WriteOper_jmp in the sdcc-sdasz80 asm writer. This fixes 
asm output for call instructions.

git-svn-id: branches/z80@44585 -
 2020-04-04 23:03:13 +00:00
nickysn
fdc24164a0 + implemented 8-bit signed comparisons as well 
git-svn-id: branches/z80@44583 -
 2020-04-04 20:59:52 +00:00
nickysn
8a1be73ce0 * also use the unsigned 8-bit comparison code for 8-bit signed equal/unequal comparisons 
git-svn-id: branches/z80@44582 -
 2020-04-04 20:28:53 +00:00
nickysn
55c18a11a0 - removed commented out code from TZ80AddNode.second_cmp 
git-svn-id: branches/z80@44581 -
 2020-04-04 20:16:11 +00:00
nickysn
9dc8744b53 - removed debug writeln 
git-svn-id: branches/z80@44580 -
 2020-04-04 20:15:10 +00:00
nickysn
59d7a45215 * generate more optimal code for unsigned 8-bit comparisons in TZ80AddNode.second_cmp 
git-svn-id: branches/z80@44579 -
 2020-04-04 20:14:31 +00:00
nickysn
5585bdb6aa + also support unsigned 8-bit > and <= in TZ80AddNode.second_cmp. All 8-bit unsigned comparisons now 
work.

git-svn-id: branches/z80@44576 -
 2020-04-04 17:49:13 +00:00
nickysn
f52f9dc56b + added a not-yet-complete implementation of TZ80AddNode.second_cmp. Only 8-bit unsigned comparison 
works for now, and only for the <,= and <> operators

git-svn-id: branches/z80@44575 -
 2020-04-04 17:15:31 +00:00
nickysn
3ed692a157 + implemented tcgz80.a_jmp_flags 
git-svn-id: branches/z80@44574 -
 2020-04-04 17:07:54 +00:00
nickysn
ff655543ed + support conditional jumps in the sdcc-sdasz80 assembler writer 
git-svn-id: branches/z80@44573 -
 2020-04-04 17:05:49 +00:00
nickysn
d05a632616 + write jump operands (not all forms supported yet) in the sdcc-sdasz80 asm output 
git-svn-id: branches/z80@44572 -
 2020-04-04 16:59:14 +00:00
nickysn
fb3a079916 * updated TAsmCond and TResFlags for the Z80 
git-svn-id: branches/z80@44571 -
 2020-04-04 16:12:47 +00:00
nickysn
99e304165e * fix for 64-bit OP_AND/OP_OR/OP_XOR in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44570 -
 2020-04-04 15:33:01 +00:00
nickysn
c0b3eb70ac + fix for 64-bit OP_NOT in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44569 -
 2020-04-04 15:30:43 +00:00
nickysn
5b8fd51b3a + implemented OP_NEG in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44568 -
 2020-04-04 15:27:28 +00:00
nickysn
a362c3247d + added instruction encoding info for all the remaining Z80 instructions 
git-svn-id: branches/z80@44567 -
 2020-04-04 13:49:07 +00:00
nickysn
c5aa1193bf + started describing the instructions encoding 
git-svn-id: branches/z80@44558 -
 2020-04-04 02:35:15 +00:00
nickysn
4027ad18e0 + added strict validation for the param types in z80ins.dat 
git-svn-id: branches/z80@44557 -
 2020-04-04 02:11:20 +00:00
nickysn
20eab5582f + generate the Z80 instruction enum and string table from z80ins.dat via a newly created tool 
git-svn-id: branches/z80@44556 -
 2020-04-04 01:36:07 +00:00
nickysn
565cc0e96b + created a parseable Z80 instruction description file, very loosely based on x86ins.dat. Parser not 
implemented yet, but will be soon.

git-svn-id: branches/z80@44554 -
 2020-04-04 00:21:50 +00:00
nickysn
9309e2c42e * replace 'add/adc/sub/sbc/and/or/xor/cp orgreg' with 'add/adc/sub/sbc/and/or/xor/cp spilltemp' in 
trgcpu.do_spill_replace

git-svn-id: branches/z80@44553 -
 2020-04-03 22:42:02 +00:00
nickysn
e43834c5d0 * replace 'inc/dec orgreg' with 'inc/dec spilltemp' in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44552 -
 2020-04-03 22:19:40 +00:00
nickysn
9d545342f8 * replace 'add/adc/sub/sbc/and/or/xor/cp A,orgreg' with 'add/adc/sub/sbc/and/or/xor/cp A,spilltemp' in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44537 -
 2020-04-03 20:05:42 +00:00