mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-24 05:59:34 +02:00
387824c1ee
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions. Fixed emission of regsets of S and D registers above 15. Fixed assembler reader for RRX shiftmode. There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader. git-svn-id: branches/laksen/armiw@29277 -
133 lines
4.1 KiB
PHP
133 lines
4.1 KiB
PHP
{ don't edit, this file is generated from armreg.dat }
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NR_NO = tregister($00000000);
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NR_R0 = tregister($01000000);
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NR_R1 = tregister($01000001);
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NR_R2 = tregister($01000002);
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NR_R3 = tregister($01000003);
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NR_R4 = tregister($01000004);
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NR_R5 = tregister($01000005);
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NR_R6 = tregister($01000006);
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NR_R7 = tregister($01000007);
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NR_R8 = tregister($01000008);
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NR_R9 = tregister($01000009);
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NR_R10 = tregister($0100000a);
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NR_R11 = tregister($0100000b);
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NR_R12 = tregister($0100000c);
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NR_R13 = tregister($0100000d);
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NR_R14 = tregister($0100000e);
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NR_R15 = tregister($0100000f);
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NR_F0 = tregister($02000000);
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NR_F1 = tregister($02000001);
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NR_F2 = tregister($02000002);
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NR_F3 = tregister($02000003);
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NR_F4 = tregister($02000004);
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NR_F5 = tregister($02000005);
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NR_F6 = tregister($02000006);
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NR_F7 = tregister($02000007);
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NR_S0 = tregister($04060000);
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NR_S1 = tregister($04060020);
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NR_D0 = tregister($04070000);
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NR_S2 = tregister($04060001);
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NR_S3 = tregister($04060021);
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NR_D1 = tregister($04070001);
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NR_S4 = tregister($04060002);
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NR_S5 = tregister($04060022);
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NR_D2 = tregister($04070002);
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NR_S6 = tregister($04060003);
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NR_S7 = tregister($04060023);
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NR_D3 = tregister($04070003);
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NR_S8 = tregister($04060004);
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NR_S9 = tregister($04060024);
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NR_D4 = tregister($04070004);
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NR_S10 = tregister($04060005);
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NR_S11 = tregister($04060025);
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NR_D5 = tregister($04070005);
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NR_S12 = tregister($04060006);
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NR_S13 = tregister($04060026);
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NR_D6 = tregister($04070006);
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NR_S14 = tregister($04060007);
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NR_S15 = tregister($04060027);
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NR_D7 = tregister($04070007);
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NR_S16 = tregister($04060008);
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NR_S17 = tregister($04060028);
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NR_D8 = tregister($04070008);
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NR_S18 = tregister($04060009);
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NR_S19 = tregister($04060029);
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NR_D9 = tregister($04070009);
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NR_S20 = tregister($0406000A);
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NR_S21 = tregister($0406002A);
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NR_D10 = tregister($0407000A);
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NR_S22 = tregister($0406000B);
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NR_S23 = tregister($0406002B);
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NR_D11 = tregister($0407000B);
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NR_S24 = tregister($0406000C);
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NR_S25 = tregister($0406002C);
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NR_D12 = tregister($0407000C);
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NR_S26 = tregister($0406000D);
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NR_S27 = tregister($0406002D);
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NR_D13 = tregister($0407000D);
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NR_S28 = tregister($0406000E);
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NR_S29 = tregister($0406002E);
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NR_D14 = tregister($0407000E);
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NR_S30 = tregister($0406000F);
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NR_S31 = tregister($0406002F);
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NR_D15 = tregister($0407000F);
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NR_D16 = tregister($04070010);
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NR_D17 = tregister($04070011);
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NR_D18 = tregister($04070012);
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NR_D19 = tregister($04070013);
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NR_D20 = tregister($04070014);
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NR_D21 = tregister($04070015);
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NR_D22 = tregister($04070016);
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NR_D23 = tregister($04070017);
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NR_D24 = tregister($04070018);
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NR_D25 = tregister($04070019);
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NR_D26 = tregister($0407001A);
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NR_D27 = tregister($0407001B);
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NR_D28 = tregister($0407001C);
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NR_D29 = tregister($0407001D);
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NR_D30 = tregister($0407001E);
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NR_D31 = tregister($0407001F);
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NR_CPSR = tregister($05000000);
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NR_FPSCR = tregister($05000001);
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NR_SPSR = tregister($05000002);
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NR_APSR_nzcv = tregister($05000003);
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NR_CR0 = tregister($05000004);
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NR_CR1 = tregister($05000005);
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NR_CR2 = tregister($05000006);
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NR_CR3 = tregister($05000007);
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NR_CR4 = tregister($05000008);
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NR_CR5 = tregister($05000009);
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NR_CR6 = tregister($0500000A);
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NR_CR7 = tregister($0500000B);
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NR_CR8 = tregister($0500000C);
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NR_CR9 = tregister($0500000D);
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NR_CR10 = tregister($0500000E);
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NR_CR11 = tregister($0500000F);
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NR_CR12 = tregister($05000010);
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NR_CR13 = tregister($05000011);
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NR_CR14 = tregister($05000012);
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NR_CR15 = tregister($05000013);
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NR_p15 = tregister($05000014);
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NR_APSR = tregister($05000015);
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NR_IPSR = tregister($05000016);
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NR_EPSR = tregister($05000017);
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NR_IEPSR = tregister($05000018);
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NR_IAPSR = tregister($05000019);
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NR_EAPSR = tregister($0500001A);
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NR_PSR = tregister($0500001B);
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NR_MSP = tregister($0500001C);
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NR_PSP = tregister($0500001D);
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NR_PRIMASK = tregister($0500001E);
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NR_BASEPRI = tregister($0500001F);
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NR_BASEPRI_MAX = tregister($05000020);
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NR_FAULTMASK = tregister($05000021);
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NR_CONTROL = tregister($05000022);
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NR_FPSID = tregister($05000023);
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NR_MVFR1 = tregister($05000024);
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NR_MVFR0 = tregister($05000025);
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NR_FPEXC = tregister($05000026);
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NR_APSR_nzcvq = tregister($05000027);
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NR_APSR_g = tregister($05000028);
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NR_APSR_nzcvqg = tregister($05000029);
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