Jonas Maebe 197f5cbec5 * let all the case code generation work with tconstexprint instead of aint, ... so it also works for 32 bit targets and a high level code generator (where aint is still 32 bit, but 64 bit operations are not decomposed) git-svn-id: trunk@41441 - (cherry picked from commit 07bd4ba517) With local change to fix compilation for x86_64 CPU		2021-08-26 23:28:28 +02:00
..
aasmcpu.pas	--- Merging r39714 into '.':	2018-09-22 12:02:55 +00:00
agarmgas.pas	------------------------------------------------------------------------	2020-09-23 09:19:51 +00:00
aoptcpu.pas	Merge of revisions 40277	2018-12-31 15:48:08 +00:00
aoptcpub.pas	* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.	2014-09-22 16:18:16 +00:00
aoptcpud.pas
armatt.inc	Add support for writeback in RFE and SRS instructions.	2015-12-26 23:53:11 +00:00
armatts.inc	Add support for writeback in RFE and SRS instructions.	2015-12-26 23:53:11 +00:00
armins.dat	Merge of commit #47207	2020-12-31 11:18:37 +00:00
armnop.inc	+ support for vmov.xx vreg,#imm on arm	2018-06-24 12:39:59 +00:00
armop.inc	Add support for writeback in RFE and SRS instructions.	2015-12-26 23:53:11 +00:00
armreg.dat	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
armtab.inc	Merge of commit #47207	2020-12-31 11:18:37 +00:00
cgcpu.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
cpubase.pas	Merge of revisions 40277	2018-12-31 15:48:08 +00:00
cpuelf.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
cpuinfo.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
cpunode.pas	* automatically generate necessary indirect symbols when a new assembler	2016-07-20 20:53:03 +00:00
cpupara.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
cpupi.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
cputarg.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00
hlcgcpu.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
itcpugas.pas	* remove unused units from uses statements	2013-01-03 23:07:09 +00:00
narmadd.pas	Merge commits 42525 and 45891 that add	2020-08-04 10:30:50 +00:00
narmcal.pas	syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed	2016-12-02 09:29:09 +00:00
narmcnv.pas	* tarmtypeconvnode.first_int_to_real should call the generic method in the parent class, if soft fpu code is generated, resolves #31350	2017-02-12 16:05:13 +00:00
narmcon.pas	* use vmov.xx to load float constants if possible	2018-06-24 12:40:00 +00:00
narminl.pas	Merge commits 42525 and 45891 that add	2020-08-04 10:30:50 +00:00
narmmat.pas	Merge commits 42525 and 45891 that add	2020-08-04 10:30:50 +00:00
narmmem.pas	* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe	2015-02-23 22:56:00 +00:00
narmset.pas	* let all the case code generation work with tconstexprint instead of aint,	2021-08-26 23:28:28 +02:00
pp.lpi.template
raarm.pas
raarmgas.pas	* factored out check to determine whether a variable can be subscripted in	2018-01-01 14:29:21 +00:00
rarmcon.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmdwa.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmnor.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmnum.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmrni.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmsri.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmsta.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmstd.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rarmsup.inc	Added some APSR register bitmask definitions.	2014-12-12 22:23:44 +00:00
rgcpu.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
symcpu.pas	* rest of the previous accidental partial commit	2019-02-07 19:56:21 +00:00
tripletcpu.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00