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229 lines
9.0 KiB
ObjectPascal
229 lines
9.0 KiB
ObjectPascal
{
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Copyright (c) 1998-2019 by Florian Klaempfl
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Generate Xtensa assembler for type converting nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpucnv;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncnv,ncgcnv;
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type
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tcputypeconvnode = class(tcgtypeconvnode)
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protected
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function first_real_to_real: tnode;override;
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procedure second_int_to_bool;override;
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procedure second_int_to_real;override;
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function first_int_to_real: tnode;override;
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end;
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implementation
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uses
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verbose,globtype,globals,symdef,aasmbase,aasmtai,aasmdata,symtable,
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defutil,
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cgbase,cgutils,
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pass_1,pass_2,procinfo,ncal,
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ncgutil,
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cpubase,cpuinfo,aasmcpu,cgobj,hlcgobj,cgcpu;
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{*****************************************************************************
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tcputypeconvnode
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*****************************************************************************}
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function tcputypeconvnode.first_real_to_real: tnode;
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begin
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if (FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) and
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not(FPUXTENSA_DOUBLE in fpu_capabilities[current_settings.fputype]) then
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begin
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case tfloatdef(left.resultdef).floattype of
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s32real:
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case tfloatdef(resultdef).floattype of
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s64real:
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result:=ctypeconvnode.create_explicit(ccallnode.createintern('float32_to_float64',ccallparanode.create(
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ctypeconvnode.create_internal(left,search_system_type('FLOAT32REC').typedef),nil)),resultdef);
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s32real:
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begin
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result:=left;
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left:=nil;
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end;
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else
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internalerror(2020092603);
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end;
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s64real:
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case tfloatdef(resultdef).floattype of
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s32real:
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result:=ctypeconvnode.create_explicit(ccallnode.createintern('float64_to_float32',ccallparanode.create(
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ctypeconvnode.create_internal(left,search_system_type('FLOAT64').typedef),nil)),resultdef);
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s64real:
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begin
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result:=left;
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left:=nil;
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end;
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else
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internalerror(2020092602);
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end;
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else
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internalerror(2020092601);
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end;
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left:=nil;
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firstpass(result);
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exit;
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end
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else
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Result := inherited first_real_to_real;
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end;
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procedure tcputypeconvnode.second_int_to_bool;
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var
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hreg1, onereg: tregister;
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href : treference;
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hlabel : tasmlabel;
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newsize : tcgsize;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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{ Explicit typecasts from any ordinal type to a boolean type
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must not change the ordinal value }
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if (nf_explicit in flags) and
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not(left.location.loc in [LOC_JUMP]) then
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begin
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location_copy(location,left.location);
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newsize:=def_cgsize(resultdef);
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{ change of size? change sign only if location is LOC_(C)REGISTER? Then we have to sign/zero-extend }
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if (tcgsize2size[newsize]<>tcgsize2size[left.location.size]) or
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((newsize<>left.location.size) and (location.loc in [LOC_REGISTER,LOC_CREGISTER])) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,true)
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else
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location.size:=newsize;
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exit;
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end;
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if (left.location.loc in [LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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onereg:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,1,onereg);
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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case left.location.loc of
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LOC_CREFERENCE,
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LOC_REFERENCE :
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begin
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if left.location.size in [OS_64,OS_S64] then
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begin
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_32,OS_32,left.location.reference,hreg1);
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href:=left.location.reference;
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inc(href.offset,4);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,href,hreg1);
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end
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else
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,left.location.size,OS_32,left.location.reference,hreg1);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_MOVNEZ,hreg1,onereg,hreg1));
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end;
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LOC_REGISTER,LOC_CREGISTER :
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begin
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if left.location.size in [OS_64,OS_S64] then
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,left.location.register64.reglo,left.location.register64.reghi,hreg1)
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else
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,left.location.size,OS_32,left.location.register,hreg1);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_MOVNEZ,hreg1,onereg,hreg1));
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end;
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LOC_JUMP :
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begin
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current_asmdata.getjumplabel(hlabel);
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cg.a_label(current_asmdata.CurrAsmList,left.location.truelabel);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,1,hreg1);
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cg.a_jmp_always(current_asmdata.CurrAsmList,hlabel);
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cg.a_label(current_asmdata.CurrAsmList,left.location.falselabel);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,0,hreg1);
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cg.a_label(current_asmdata.CurrAsmList,hlabel);
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end;
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else
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internalerror(2020031504);
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end;
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if (is_cbool(resultdef)) then
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,location.size,hreg1,hreg1);
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{$ifndef cpu64bitalu}
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if (location.size in [OS_64,OS_S64]) then
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begin
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location.register64.reglo:=hreg1;
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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if (is_cbool(resultdef)) then
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{ reglo is either 0 or -1 -> reghi has to become the same }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_32,OS_32,location.register64.reglo,location.register64.reghi)
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else
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{ unsigned }
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reghi);
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end
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else
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{$endif cpu64bitalu}
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location.register:=hreg1;
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end;
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function tcputypeconvnode.first_int_to_real: tnode;
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var
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fname: string[19];
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) or
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(current_settings.fputype=fpu_soft) or
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not(FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) or
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((is_double(resultdef)) and not(FPUXTENSA_DOUBLE in fpu_capabilities[current_settings.fputype])) or
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is_64bitint(left.resultdef) or
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is_currency(left.resultdef) or
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(is_32bit(left.resultdef) and not(is_signed(left.resultdef))) then
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result:=inherited first_int_to_real
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else
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begin
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{ other integers are supposed to be 32 bit }
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inserttypeconv(left,s32inttype);
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firstpass(left);
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result:=nil;
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expectloc:=LOC_FPUREGISTER;
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end;
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end;
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procedure tcputypeconvnode.second_int_to_real;
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var
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ai: taicpu;
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,s32inttype,true);
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ai:=taicpu.op_reg_reg_const(A_FLOAT,location.register,left.location.register,0);
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ai.oppostfix:=PF_S;
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current_asmdata.CurrAsmList.concat(ai);
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end;
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begin
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ctypeconvnode:=tcputypeconvnode;
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end.
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