mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-22 04:49:39 +02:00
8382c6f586
Modified low-level startup code for RISCV32 embedded microcontrollers to allow user code override of reset handlers for non-power-up reset events as well as enabling user code override handlers for all 255 possible interrupt vectors. Separated out the low-level startup memory init into a callable procedure to allow users that have caught reset events to init memory again if needed. Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
639 lines
24 KiB
ObjectPascal
639 lines
24 KiB
ObjectPascal
{$IFNDEF FPC_DOTTEDUNITS}
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unit fe310g002;
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{$ENDIF FPC_DOTTEDUNITS}
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interface
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{$PACKRECORDS 2}
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{$GOTO ON}
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{$MODESWITCH ADVANCEDRECORDS}
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type
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TIRQn_Enum = (
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NonMaskableInt_IRQn = -14, // 2 Non Maskable Interrupt
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MemoryManagement_IRQn = -12, // 4 Cortex-M4 Memory Management Interrupt
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BusFault_IRQn = -11, // 5 Cortex-M4 Bus Fault Interrupt
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UsageFault_IRQn = -10, // 6 Cortex-M4 Usage Fault Interrupt
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SVCall_IRQn = -5, // 11 Cortex-M4 SV Call Interrupt
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DebugMonitor_IRQn = -4, // 12 Cortex-M4 Debug Monitor Interrupt
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PendSV_IRQn = -2, // 14 Cortex-M4 Pend SV Interrupt
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SysTick_IRQn = -1, // 15 Cortex-M4 System Tick Interrupt
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WWDG_IRQn = 0, // Window WatchDog Interrupt
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PVD_IRQn = 1, // PVD through EXTI Line detection Interrupt
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TAMP_STAMP_IRQn = 2, // Tamper and TimeStamp interrupts through the EXTI line
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RTC_WKUP_IRQn = 3, // RTC Wakeup interrupt through the EXTI line
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FLASH_IRQn = 4, // FLASH global Interrupt
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RCC_IRQn = 5, // RCC global Interrupt
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EXTI0_IRQn = 6, // EXTI Line0 Interrupt
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EXTI1_IRQn = 7, // EXTI Line1 Interrupt
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EXTI2_IRQn = 8, // EXTI Line2 Interrupt
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EXTI3_IRQn = 9, // EXTI Line3 Interrupt
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EXTI4_IRQn = 10, // EXTI Line4 Interrupt
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DMA1_Stream0_IRQn = 11, // DMA1 Stream 0 global Interrupt
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DMA1_Stream1_IRQn = 12, // DMA1 Stream 1 global Interrupt
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DMA1_Stream2_IRQn = 13, // DMA1 Stream 2 global Interrupt
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DMA1_Stream3_IRQn = 14, // DMA1 Stream 3 global Interrupt
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DMA1_Stream4_IRQn = 15, // DMA1 Stream 4 global Interrupt
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DMA1_Stream5_IRQn = 16, // DMA1 Stream 5 global Interrupt
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DMA1_Stream6_IRQn = 17, // DMA1 Stream 6 global Interrupt
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ADC_IRQn = 18, // ADC1, ADC2 and ADC3 global Interrupts
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CAN1_TX_IRQn = 19, // CAN1 TX Interrupt
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CAN1_RX0_IRQn = 20, // CAN1 RX0 Interrupt
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CAN1_RX1_IRQn = 21, // CAN1 RX1 Interrupt
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CAN1_SCE_IRQn = 22, // CAN1 SCE Interrupt
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EXTI9_5_IRQn = 23, // External Line[9:5] Interrupts
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TIM1_BRK_TIM9_IRQn = 24, // TIM1 Break interrupt and TIM9 global interrupt
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TIM1_UP_TIM10_IRQn = 25, // TIM1 Update Interrupt and TIM10 global interrupt
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TIM1_TRG_COM_TIM11_IRQn = 26, // TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt
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TIM1_CC_IRQn = 27, // TIM1 Capture Compare Interrupt
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TIM2_IRQn = 28, // TIM2 global Interrupt
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TIM3_IRQn = 29, // TIM3 global Interrupt
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TIM4_IRQn = 30, // TIM4 global Interrupt
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I2C1_EV_IRQn = 31, // I2C1 Event Interrupt
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I2C1_ER_IRQn = 32, // I2C1 Error Interrupt
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I2C2_EV_IRQn = 33, // I2C2 Event Interrupt
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I2C2_ER_IRQn = 34, // I2C2 Error Interrupt
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SPI1_IRQn = 35, // SPI1 global Interrupt
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SPI2_IRQn = 36, // SPI2 global Interrupt
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USART1_IRQn = 37, // USART1 global Interrupt
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USART2_IRQn = 38, // USART2 global Interrupt
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USART3_IRQn = 39, // USART3 global Interrupt
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EXTI15_10_IRQn = 40, // External Line[15:10] Interrupts
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RTC_Alarm_IRQn = 41, // RTC Alarm (A and B) through EXTI Line Interrupt
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OTG_FS_WKUP_IRQn = 42, // USB OTG FS Wakeup through EXTI line interrupt
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TIM8_BRK_TIM12_IRQn = 43, // TIM8 Break Interrupt and TIM12 global interrupt
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TIM8_UP_TIM13_IRQn = 44, // TIM8 Update Interrupt and TIM13 global interrupt
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TIM8_TRG_COM_TIM14_IRQn = 45, // TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
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TIM8_CC_IRQn = 46, // TIM8 Capture Compare Interrupt
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DMA1_Stream7_IRQn = 47, // DMA1 Stream7 Interrupt
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FSMC_IRQn = 48, // FSMC global Interrupt
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SDIO_IRQn = 49, // SDIO global Interrupt
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TIM5_IRQn = 50, // TIM5 global Interrupt
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SPI3_IRQn = 51, // SPI3 global Interrupt
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UART4_IRQn = 52, // UART4 global Interrupt
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UART5_IRQn = 53, // UART5 global Interrupt
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TIM6_DAC_IRQn = 54, // TIM6 global and DAC1&2 underrun error interrupts
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TIM7_IRQn = 55, // TIM7 global interrupt
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DMA2_Stream0_IRQn = 56, // DMA2 Stream 0 global Interrupt
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DMA2_Stream1_IRQn = 57, // DMA2 Stream 1 global Interrupt
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DMA2_Stream2_IRQn = 58, // DMA2 Stream 2 global Interrupt
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DMA2_Stream3_IRQn = 59, // DMA2 Stream 3 global Interrupt
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DMA2_Stream4_IRQn = 60, // DMA2 Stream 4 global Interrupt
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ETH_IRQn = 61, // Ethernet global Interrupt
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ETH_WKUP_IRQn = 62, // Ethernet Wakeup through EXTI line Interrupt
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CAN2_TX_IRQn = 63, // CAN2 TX Interrupt
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CAN2_RX0_IRQn = 64, // CAN2 RX0 Interrupt
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CAN2_RX1_IRQn = 65, // CAN2 RX1 Interrupt
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CAN2_SCE_IRQn = 66, // CAN2 SCE Interrupt
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OTG_FS_IRQn = 67, // USB OTG FS global Interrupt
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DMA2_Stream5_IRQn = 68, // DMA2 Stream 5 global interrupt
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DMA2_Stream6_IRQn = 69, // DMA2 Stream 6 global interrupt
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DMA2_Stream7_IRQn = 70, // DMA2 Stream 7 global interrupt
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USART6_IRQn = 71, // USART6 global interrupt
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I2C3_EV_IRQn = 72, // I2C3 event interrupt
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I2C3_ER_IRQn = 73, // I2C3 error interrupt
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OTG_HS_EP1_OUT_IRQn = 74, // USB OTG HS End Point 1 Out global interrupt
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OTG_HS_EP1_IN_IRQn = 75, // USB OTG HS End Point 1 In global interrupt
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OTG_HS_WKUP_IRQn = 76, // USB OTG HS Wakeup through EXTI interrupt
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OTG_HS_IRQn = 77, // USB OTG HS global interrupt
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DCMI_IRQn = 78, // DCMI global interrupt
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HASH_RNG_IRQn = 80, // Hash and RNG global interrupt
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FPU_IRQn = 81 // FPU global interrupt
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);
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TADC_Registers = record
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end;
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TGPIO_Registers = record
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VALUE : longWord;
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INPUT_EN : longword;
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OUTPUT_EN : longword;
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PORT : longword;
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PUE : longword;
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DS : longword;
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RISE_IE : longword;
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RISE_IP : longword;
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FALL_IE : longword;
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FALL_IP : longword;
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HIGH_IE : longword;
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HIGH_IP : longword;
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LOW_IE : longword;
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LOW_IP : longword;
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IOF_EN : longword;
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IOF_SEL : longword;
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OUT_XOR : longword;
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end;
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// Watchdog Registers
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TWDT_Registers = record
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WDOGCFG : longWord;
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RESERVED0 : longWord;
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WDOGCOUNT : longWord;
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Reserved1 : longWord;
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WDOGS : longWord;
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RESERVED2 : longWord;
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WDOGFEED : longWord;
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WDOGKEY : longWord;
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WDOGCMP : longWord;
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end;
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// RTC Registers
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TRTCRegisters = record
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RTCCFG : longWord;
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RESERVED0 : longWord;
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RTCLO_HI : longWord;
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RESERVED1 : longWord;
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RTCS : longWord;
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RESERVED2 : longWord;
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RESERVED3 : longWord;
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RESERVED4 : longWord;
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RTCCMP : longWord;
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end;
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TLFROSC_Registers = record
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LFROSCCFG : longWord;
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end;
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// Backup Registers
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TBackup_Registers = record
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BACKUP : array[0..31] of longWord;
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end;
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// PMU Registers
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TPMU_Registers = record
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PMU_WAKEUP_BASE : longWord;
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RESERVED0 : array[1..7] of longWord;
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PWM_SLEEP_BASE : longWord;
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RESERVED1 : array[1..7] of longWord;
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PMUIE : longWord;
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PMUCAUSE : longWord;
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PMUSLEEP : longWord;
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PMUKEY : longWord;
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end;
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TI2C_Registers = record
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PRESCALE_LOW : longWord;
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PRESCALE_HIGH : longWord;
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CONTROL :longWord;
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TRANSMIT_RECEIVE : longWord;
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COMMAND_STATUS : longWord;
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end;
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TPWM_Registers = record
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PWMCFG : longWord;
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RESERVED0 : longWord;
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PWMCOUNT : longWord;
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RESERVED1 : longWord;
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PWMS : longWord;
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RESERVED2 : array[1..3] of longWord;
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PWMCMP : array[0..3] of longWord;
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end;
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TSPI_Registers = record
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SCKDIV : longWord;
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SCKMODE : longWord;
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RESERVED0 : longWord;
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RESERVED1 : longWord;
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CSID : longWord;
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CSDEF : longWord;
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CSMODE : longWord;
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RESERVED2 : longWord;
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RESERVED3 : array[1..2] of longWord;
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DELAY0 : longWord;
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DELAY1 : longWord;
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RESERVED4 : array[1..4] of longWord;
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FMT : longWord;
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RESERVED5 : longWord;
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TXDATA : longWord;
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RXDATA : longWord;
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TXMARK : longWord;
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RESERVED6 : longWord;
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RXMARK : longWord;
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RESERVED7 : array[1..2] of longWord;
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// TODO: Only include if the device supports a direct-map flash interface
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FCTRL : longWord;
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FFMT : longWord;
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RESERVED8 : array[1..2] of longWord;
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IE : longWord;
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RESERVED9 : longWord;
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IP : longWord;
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end;
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TUART_Registers = record
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TXDATA : longWord;
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RXDATA : longWord;
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TXCTRL : longWord;
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RXCTRL : longWord;
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IE : longWord;
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IP : longWord;
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&DIV : longWord;
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end;
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const
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GPIOA_BASE = $10012000;
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UART0_BASE = $10013000;
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SPI0_BASE = $10014000;
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PWM0_BASE = $10015000;
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I2C0_BASE = $10016000;
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UART1_BASE = $10023000;
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SPI1_BASE = $10024000;
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PWM1_BASE = $10025000;
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SPI2_BASE = $10034000;
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PWM2_BASE = $10035000;
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DTIM_BASE = $80000000;
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var
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GPIOA : TGPIO_Registers absolute GPIOA_BASE;
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I2C0 : TI2C_Registers absolute I2C0_BASE;
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PWM0 : TPWM_Registers absolute PWM0_BASE;
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PWM1 : TPWM_Registers absolute PWM1_BASE;
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PWM2 : TPWM_Registers absolute PWM2_BASE;
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SPI0 : TSPI_Registers absolute SPI0_BASE;
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SPI1 : TSPI_Registers absolute SPI1_BASE;
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SPI2 : TSPI_Registers absolute SPI2_BASE;
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UART0 : TUART_Registers absolute UART0_BASE;
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UART1 : TUART_Registers absolute UART1_BASE;
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procedure InitMemAndStart; noreturn;
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implementation
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procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
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procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
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procedure BusFault_interrupt; external name 'BusFault_interrupt';
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procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
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procedure SVCall_interrupt; external name 'SVCall_interrupt';
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procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
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procedure PendSV_interrupt; external name 'PendSV_interrupt';
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procedure SysTick_interrupt; external name 'SysTick_interrupt';
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procedure WWDG_interrupt; external name 'WWDG_interrupt';
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procedure PVD_interrupt; external name 'PVD_interrupt';
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procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt';
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procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt';
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procedure FLASH_interrupt; external name 'FLASH_interrupt';
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procedure RCC_interrupt; external name 'RCC_interrupt';
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procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
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procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
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procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
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procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
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procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
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procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt';
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procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt';
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procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt';
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procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt';
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procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt';
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procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt';
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procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt';
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procedure ADC_interrupt; external name 'ADC_interrupt';
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procedure CAN1_TX_interrupt; external name 'CAN1_TX_interrupt';
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procedure CAN1_RX0_interrupt; external name 'CAN1_RX0_interrupt';
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procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
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procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
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procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
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procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt';
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procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt';
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procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt';
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procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
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procedure TIM2_interrupt; external name 'TIM2_interrupt';
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procedure TIM3_interrupt; external name 'TIM3_interrupt';
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procedure TIM4_interrupt; external name 'TIM4_interrupt';
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procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
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procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
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procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
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procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
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procedure SPI1_interrupt; external name 'SPI1_interrupt';
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procedure SPI2_interrupt; external name 'SPI2_interrupt';
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procedure USART1_interrupt; external name 'USART1_interrupt';
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procedure USART2_interrupt; external name 'USART2_interrupt';
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procedure USART3_interrupt; external name 'USART3_interrupt';
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procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
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procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt';
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procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt';
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procedure TIM8_BRK_TIM12_interrupt; external name 'TIM8_BRK_TIM12_interrupt';
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procedure TIM8_UP_TIM13_interrupt; external name 'TIM8_UP_TIM13_interrupt';
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procedure TIM8_TRG_COM_TIM14_interrupt; external name 'TIM8_TRG_COM_TIM14_interrupt';
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procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt';
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procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt';
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procedure FSMC_interrupt; external name 'FSMC_interrupt';
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procedure SDIO_interrupt; external name 'SDIO_interrupt';
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procedure TIM5_interrupt; external name 'TIM5_interrupt';
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procedure SPI3_interrupt; external name 'SPI3_interrupt';
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procedure UART4_interrupt; external name 'UART4_interrupt';
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procedure UART5_interrupt; external name 'UART5_interrupt';
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procedure TIM6_DAC_interrupt; external name 'TIM6_DAC_interrupt';
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procedure TIM7_interrupt; external name 'TIM7_interrupt';
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procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt';
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procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt';
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procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt';
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procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt';
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procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt';
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procedure ETH_interrupt; external name 'ETH_interrupt';
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procedure ETH_WKUP_interrupt; external name 'ETH_WKUP_interrupt';
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procedure CAN2_TX_interrupt; external name 'CAN2_TX_interrupt';
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procedure CAN2_RX0_interrupt; external name 'CAN2_RX0_interrupt';
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procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt';
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procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt';
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procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt';
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procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt';
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procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt';
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procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt';
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procedure USART6_interrupt; external name 'USART6_interrupt';
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procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt';
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procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt';
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procedure OTG_HS_EP1_OUT_interrupt; external name 'OTG_HS_EP1_OUT_interrupt';
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procedure OTG_HS_EP1_IN_interrupt; external name 'OTG_HS_EP1_IN_interrupt';
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procedure OTG_HS_WKUP_interrupt; external name 'OTG_HS_WKUP_interrupt';
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procedure OTG_HS_interrupt; external name 'OTG_HS_interrupt';
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procedure DCMI_interrupt; external name 'DCMI_interrupt';
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procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt';
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procedure FPU_interrupt; external name 'FPU_interrupt';
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procedure ResetISR; external name 'ResetISR';
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procedure HandleArchSpecificReset; noreturn;
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begin
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InitMemAndStart
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end;
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{$i riscv32_start.inc}
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procedure Vectors; assembler; nostackframe;
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label interrupt_vectors;
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asm
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.section ".init.interrupt_vectors"
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interrupt_vectors:
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jal _stack_top
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jal HandleArchSpecificReset
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jal NonMaskableInt_interrupt
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.long 0
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.long MemoryManagement_interrupt
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.long BusFault_interrupt
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.long UsageFault_interrupt
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.long 0
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.long 0
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.long 0
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.long 0
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.long SVCall_interrupt
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.long DebugMonitor_interrupt
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.long 0
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.long PendSV_interrupt
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.long SysTick_interrupt
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.long WWDG_interrupt
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.long PVD_interrupt
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.long TAMP_STAMP_interrupt
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.long RTC_WKUP_interrupt
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.long FLASH_interrupt
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.long RCC_interrupt
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.long EXTI0_interrupt
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.long EXTI1_interrupt
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.long EXTI2_interrupt
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.long EXTI3_interrupt
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.long EXTI4_interrupt
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.long DMA1_Stream0_interrupt
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.long DMA1_Stream1_interrupt
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.long DMA1_Stream2_interrupt
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.long DMA1_Stream3_interrupt
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.long DMA1_Stream4_interrupt
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.long DMA1_Stream5_interrupt
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.long DMA1_Stream6_interrupt
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.long ADC_interrupt
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.long CAN1_TX_interrupt
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.long CAN1_RX0_interrupt
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.long CAN1_RX1_interrupt
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.long CAN1_SCE_interrupt
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.long EXTI9_5_interrupt
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.long TIM1_BRK_TIM9_interrupt
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.long TIM1_UP_TIM10_interrupt
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.long TIM1_TRG_COM_TIM11_interrupt
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.long TIM1_CC_interrupt
|
|
.long TIM2_interrupt
|
|
.long TIM3_interrupt
|
|
.long TIM4_interrupt
|
|
.long I2C1_EV_interrupt
|
|
.long I2C1_ER_interrupt
|
|
.long I2C2_EV_interrupt
|
|
.long I2C2_ER_interrupt
|
|
.long SPI1_interrupt
|
|
.long SPI2_interrupt
|
|
.long USART1_interrupt
|
|
.long USART2_interrupt
|
|
.long USART3_interrupt
|
|
.long EXTI15_10_interrupt
|
|
.long RTC_Alarm_interrupt
|
|
.long OTG_FS_WKUP_interrupt
|
|
.long TIM8_BRK_TIM12_interrupt
|
|
.long TIM8_UP_TIM13_interrupt
|
|
.long TIM8_TRG_COM_TIM14_interrupt
|
|
.long TIM8_CC_interrupt
|
|
.long DMA1_Stream7_interrupt
|
|
.long FSMC_interrupt
|
|
.long SDIO_interrupt
|
|
.long TIM5_interrupt
|
|
.long SPI3_interrupt
|
|
.long UART4_interrupt
|
|
.long UART5_interrupt
|
|
.long TIM6_DAC_interrupt
|
|
.long TIM7_interrupt
|
|
.long DMA2_Stream0_interrupt
|
|
.long DMA2_Stream1_interrupt
|
|
.long DMA2_Stream2_interrupt
|
|
.long DMA2_Stream3_interrupt
|
|
.long DMA2_Stream4_interrupt
|
|
.long ETH_interrupt
|
|
.long ETH_WKUP_interrupt
|
|
.long CAN2_TX_interrupt
|
|
.long CAN2_RX0_interrupt
|
|
.long CAN2_RX1_interrupt
|
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.long CAN2_SCE_interrupt
|
|
.long OTG_FS_interrupt
|
|
.long DMA2_Stream5_interrupt
|
|
.long DMA2_Stream6_interrupt
|
|
.long DMA2_Stream7_interrupt
|
|
.long USART6_interrupt
|
|
.long I2C3_EV_interrupt
|
|
.long I2C3_ER_interrupt
|
|
.long OTG_HS_EP1_OUT_interrupt
|
|
.long OTG_HS_EP1_IN_interrupt
|
|
.long OTG_HS_WKUP_interrupt
|
|
.long OTG_HS_interrupt
|
|
.long DCMI_interrupt
|
|
.long 0
|
|
.long HASH_RNG_interrupt
|
|
.long FPU_interrupt
|
|
.weak NonMaskableInt_interrupt
|
|
.weak MemoryManagement_interrupt
|
|
.weak BusFault_interrupt
|
|
.weak UsageFault_interrupt
|
|
.weak SVCall_interrupt
|
|
.weak DebugMonitor_interrupt
|
|
.weak PendSV_interrupt
|
|
.weak SysTick_interrupt
|
|
.weak WWDG_interrupt
|
|
.weak PVD_interrupt
|
|
.weak TAMP_STAMP_interrupt
|
|
.weak RTC_WKUP_interrupt
|
|
.weak FLASH_interrupt
|
|
.weak RCC_interrupt
|
|
.weak EXTI0_interrupt
|
|
.weak EXTI1_interrupt
|
|
.weak EXTI2_interrupt
|
|
.weak EXTI3_interrupt
|
|
.weak EXTI4_interrupt
|
|
.weak DMA1_Stream0_interrupt
|
|
.weak DMA1_Stream1_interrupt
|
|
.weak DMA1_Stream2_interrupt
|
|
.weak DMA1_Stream3_interrupt
|
|
.weak DMA1_Stream4_interrupt
|
|
.weak DMA1_Stream5_interrupt
|
|
.weak DMA1_Stream6_interrupt
|
|
.weak ADC_interrupt
|
|
.weak CAN1_TX_interrupt
|
|
.weak CAN1_RX0_interrupt
|
|
.weak CAN1_RX1_interrupt
|
|
.weak CAN1_SCE_interrupt
|
|
.weak EXTI9_5_interrupt
|
|
.weak TIM1_BRK_TIM9_interrupt
|
|
.weak TIM1_UP_TIM10_interrupt
|
|
.weak TIM1_TRG_COM_TIM11_interrupt
|
|
.weak TIM1_CC_interrupt
|
|
.weak TIM2_interrupt
|
|
.weak TIM3_interrupt
|
|
.weak TIM4_interrupt
|
|
.weak I2C1_EV_interrupt
|
|
.weak I2C1_ER_interrupt
|
|
.weak I2C2_EV_interrupt
|
|
.weak I2C2_ER_interrupt
|
|
.weak SPI1_interrupt
|
|
.weak SPI2_interrupt
|
|
.weak USART1_interrupt
|
|
.weak USART2_interrupt
|
|
.weak USART3_interrupt
|
|
.weak EXTI15_10_interrupt
|
|
.weak RTC_Alarm_interrupt
|
|
.weak OTG_FS_WKUP_interrupt
|
|
.weak TIM8_BRK_TIM12_interrupt
|
|
.weak TIM8_UP_TIM13_interrupt
|
|
.weak TIM8_TRG_COM_TIM14_interrupt
|
|
.weak TIM8_CC_interrupt
|
|
.weak DMA1_Stream7_interrupt
|
|
.weak FSMC_interrupt
|
|
.weak SDIO_interrupt
|
|
.weak TIM5_interrupt
|
|
.weak SPI3_interrupt
|
|
.weak UART4_interrupt
|
|
.weak UART5_interrupt
|
|
.weak TIM6_DAC_interrupt
|
|
.weak TIM7_interrupt
|
|
.weak DMA2_Stream0_interrupt
|
|
.weak DMA2_Stream1_interrupt
|
|
.weak DMA2_Stream2_interrupt
|
|
.weak DMA2_Stream3_interrupt
|
|
.weak DMA2_Stream4_interrupt
|
|
.weak ETH_interrupt
|
|
.weak ETH_WKUP_interrupt
|
|
.weak CAN2_TX_interrupt
|
|
.weak CAN2_RX0_interrupt
|
|
.weak CAN2_RX1_interrupt
|
|
.weak CAN2_SCE_interrupt
|
|
.weak OTG_FS_interrupt
|
|
.weak DMA2_Stream5_interrupt
|
|
.weak DMA2_Stream6_interrupt
|
|
.weak DMA2_Stream7_interrupt
|
|
.weak USART6_interrupt
|
|
.weak I2C3_EV_interrupt
|
|
.weak I2C3_ER_interrupt
|
|
.weak OTG_HS_EP1_OUT_interrupt
|
|
.weak OTG_HS_EP1_IN_interrupt
|
|
.weak OTG_HS_WKUP_interrupt
|
|
.weak OTG_HS_interrupt
|
|
.weak DCMI_interrupt
|
|
.weak HASH_RNG_interrupt
|
|
.weak FPU_interrupt
|
|
.set NonMaskableInt_interrupt, HaltProc
|
|
.set MemoryManagement_interrupt, HaltProc
|
|
.set BusFault_interrupt, HaltProc
|
|
.set UsageFault_interrupt, HaltProc
|
|
.set SVCall_interrupt, HaltProc
|
|
.set DebugMonitor_interrupt, HaltProc
|
|
.set PendSV_interrupt, HaltProc
|
|
.set SysTick_interrupt, HaltProc
|
|
.set WWDG_interrupt, HaltProc
|
|
.set PVD_interrupt, HaltProc
|
|
.set TAMP_STAMP_interrupt, HaltProc
|
|
.set RTC_WKUP_interrupt, HaltProc
|
|
.set FLASH_interrupt, HaltProc
|
|
.set RCC_interrupt, HaltProc
|
|
.set EXTI0_interrupt, HaltProc
|
|
.set EXTI1_interrupt, HaltProc
|
|
.set EXTI2_interrupt, HaltProc
|
|
.set EXTI3_interrupt, HaltProc
|
|
.set EXTI4_interrupt, HaltProc
|
|
.set DMA1_Stream0_interrupt, HaltProc
|
|
.set DMA1_Stream1_interrupt, HaltProc
|
|
.set DMA1_Stream2_interrupt, HaltProc
|
|
.set DMA1_Stream3_interrupt, HaltProc
|
|
.set DMA1_Stream4_interrupt, HaltProc
|
|
.set DMA1_Stream5_interrupt, HaltProc
|
|
.set DMA1_Stream6_interrupt, HaltProc
|
|
.set ADC_interrupt, HaltProc
|
|
.set CAN1_TX_interrupt, HaltProc
|
|
.set CAN1_RX0_interrupt, HaltProc
|
|
.set CAN1_RX1_interrupt, HaltProc
|
|
.set CAN1_SCE_interrupt, HaltProc
|
|
.set EXTI9_5_interrupt, HaltProc
|
|
.set TIM1_BRK_TIM9_interrupt, HaltProc
|
|
.set TIM1_UP_TIM10_interrupt, HaltProc
|
|
.set TIM1_TRG_COM_TIM11_interrupt, HaltProc
|
|
.set TIM1_CC_interrupt, HaltProc
|
|
.set TIM2_interrupt, HaltProc
|
|
.set TIM3_interrupt, HaltProc
|
|
.set TIM4_interrupt, HaltProc
|
|
.set I2C1_EV_interrupt, HaltProc
|
|
.set I2C1_ER_interrupt, HaltProc
|
|
.set I2C2_EV_interrupt, HaltProc
|
|
.set I2C2_ER_interrupt, HaltProc
|
|
.set SPI1_interrupt, HaltProc
|
|
.set SPI2_interrupt, HaltProc
|
|
.set USART1_interrupt, HaltProc
|
|
.set USART2_interrupt, HaltProc
|
|
.set USART3_interrupt, HaltProc
|
|
.set EXTI15_10_interrupt, HaltProc
|
|
.set RTC_Alarm_interrupt, HaltProc
|
|
.set OTG_FS_WKUP_interrupt, HaltProc
|
|
.set TIM8_BRK_TIM12_interrupt, HaltProc
|
|
.set TIM8_UP_TIM13_interrupt, HaltProc
|
|
.set TIM8_TRG_COM_TIM14_interrupt, HaltProc
|
|
.set TIM8_CC_interrupt, HaltProc
|
|
.set DMA1_Stream7_interrupt, HaltProc
|
|
.set FSMC_interrupt, HaltProc
|
|
.set SDIO_interrupt, HaltProc
|
|
.set TIM5_interrupt, HaltProc
|
|
.set SPI3_interrupt, HaltProc
|
|
.set UART4_interrupt, HaltProc
|
|
.set UART5_interrupt, HaltProc
|
|
.set TIM6_DAC_interrupt, HaltProc
|
|
.set TIM7_interrupt, HaltProc
|
|
.set DMA2_Stream0_interrupt, HaltProc
|
|
.set DMA2_Stream1_interrupt, HaltProc
|
|
.set DMA2_Stream2_interrupt, HaltProc
|
|
.set DMA2_Stream3_interrupt, HaltProc
|
|
.set DMA2_Stream4_interrupt, HaltProc
|
|
.set ETH_interrupt, HaltProc
|
|
.set ETH_WKUP_interrupt, HaltProc
|
|
.set CAN2_TX_interrupt, HaltProc
|
|
.set CAN2_RX0_interrupt, HaltProc
|
|
.set CAN2_RX1_interrupt, HaltProc
|
|
.set CAN2_SCE_interrupt, HaltProc
|
|
.set OTG_FS_interrupt, HaltProc
|
|
.set DMA2_Stream5_interrupt, HaltProc
|
|
.set DMA2_Stream6_interrupt, HaltProc
|
|
.set DMA2_Stream7_interrupt, HaltProc
|
|
.set USART6_interrupt, HaltProc
|
|
.set I2C3_EV_interrupt, HaltProc
|
|
.set I2C3_ER_interrupt, HaltProc
|
|
.set OTG_HS_EP1_OUT_interrupt, HaltProc
|
|
.set OTG_HS_EP1_IN_interrupt, HaltProc
|
|
.set OTG_HS_WKUP_interrupt, HaltProc
|
|
.set OTG_HS_interrupt, HaltProc
|
|
.set DCMI_interrupt, HaltProc
|
|
.set HASH_RNG_interrupt, HaltProc
|
|
.set FPU_interrupt, HaltProc
|
|
.text
|
|
end;
|
|
end.
|