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https://gitlab.com/freepascal.org/fpc/source.git
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8382c6f586
Modified low-level startup code for RISCV32 embedded microcontrollers to allow user code override of reset handlers for non-power-up reset events as well as enabling user code override handlers for all 255 possible interrupt vectors. Separated out the low-level startup memory init into a callable procedure to allow users that have caught reset events to init memory again if needed. Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
289 lines
8.5 KiB
ObjectPascal
289 lines
8.5 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit the GAS asm writers for Risc-V32/Risc-V64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{****************************************************************************}
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{ Helper routines for Instruction Writer }
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{****************************************************************************}
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unit agrvgas;
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{$i fpcdefs.inc}
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interface
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uses
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systems,aasmbase,
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aasmtai,aasmdata,
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aggas,
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assemble,
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cpubase,cgutils,
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globtype;
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type
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TRVInstrWriter=class(TCPUInstrWriter)
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procedure WriteInstruction(hp : tai);override;
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end;
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TRVGNUAssembler=class(TGNUassembler)
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constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
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function MakeCmdLine: TCmdStr; override;
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end;
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implementation
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uses
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cutils,globals,verbose,
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cgbase,
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itcpugas,cpuinfo,
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aasmcpu;
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function getreferencestring(asminfo: pasminfo; var ref : treference) : string;
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var
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s : string;
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begin
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with ref do
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begin
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if ((offset < -2048) or (offset > 2047)) and
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(refaddr = addr_no) then
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internalerror(2006052501);
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case refaddr of
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addr_no:
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s := '';
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addr_pic_no_got:
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internalerror(2016060501);
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else
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begin
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s :='';
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if not(refaddr in [addr_no,addr_pic_no_got,addr_plt]) then
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s := s+'(';
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if assigned(symbol) then
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begin
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if asminfo^.dollarsign<>'$' then
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begin
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s:=s+ApplyAsmSymbolRestrictions(symbol.name);
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if assigned(relsymbol) then
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s:=s+'-'+ApplyAsmSymbolRestrictions(relsymbol.name)
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end
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else
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begin
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s:=s+symbol.name;
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if assigned(relsymbol) then
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s:=s+'-'+relsymbol.name;
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end;
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end;
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end;
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end;
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if offset<0 then
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s:=s+tostr(offset)
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else
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if (offset>0) then
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begin
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if assigned(symbol) then
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s:=s+'+'+tostr(offset)
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else
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s:=s+tostr(offset);
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end;
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if not(refaddr in [addr_no,addr_pic_no_got,addr_plt]) then
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begin
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s := s+')';
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end;
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if (index=NR_NO) then
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begin
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if offset=0 then
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begin
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if not (assigned(symbol)) then
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s:=s+'0';
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end;
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if (base<>NR_NO) then
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s:=s+'('+gas_regname(base)+')'
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else if not assigned(symbol) then
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s:=s+'(0)';
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end
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else if (index<>NR_NO) and (base<>NR_NO) then
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begin
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if (offset=0) then
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s:=s+gas_regname(base)+','+gas_regname(index)
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else
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internalerror(2006052502);
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end
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else
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Internalerror(2021030602);
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case refaddr of
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addr_lo12: s:='%lo'+s;
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addr_hi20: s:='%hi'+s;
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addr_pcrel_lo12: s:='%pcrel_lo'+s;
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addr_pcrel_hi20: s:='%pcrel_hi'+s;
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addr_got_pcrel_hi: s:='%got_pcrel_hi'+s;
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addr_plt: s:=s+'@plt';
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else
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;
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end;
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end;
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getreferencestring:=s;
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end;
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function getopstr(asminfo: pasminfo; const o:toper) : string;
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var
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hs : string;
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begin
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case o.typ of
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top_reg:
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getopstr:=gas_regname(o.reg);
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top_const:
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getopstr:=tostr(longint(o.val));
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top_ref:
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if o.ref^.refaddr=addr_full then
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begin
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hs:=o.ref^.symbol.name;
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if asminfo^.dollarsign<>'$' then
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hs:=ApplyAsmSymbolRestrictions(hs);
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if o.ref^.offset>0 then
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hs:=hs+'+'+tostr(o.ref^.offset)
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else
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if o.ref^.offset<0 then
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hs:=hs+tostr(o.ref^.offset);
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getopstr:=hs;
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end
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else
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getopstr:=getreferencestring(asminfo,o.ref^);
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top_fenceflags:
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begin
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getopstr:='';
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if ffI in o.fenceflags then getopstr:=getopstr+'i';
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if ffO in o.fenceflags then getopstr:=getopstr+'o';
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if ffR in o.fenceflags then getopstr:=getopstr+'r';
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if ffW in o.fenceflags then getopstr:=getopstr+'w';
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end;
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top_roundingmode:
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getopstr:=roundingmode2str[o.roundingmode];
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else
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internalerror(2002070604);
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end;
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end;
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Procedure TRVInstrWriter.WriteInstruction(hp : tai);
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var op: TAsmOp;
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s: string;
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i: byte;
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sep: string[3];
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begin
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s:=#9+gas_op2str[taicpu(hp).opcode];
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if taicpu(hp).condition<>C_None then
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s:=s+cond2str[taicpu(hp).condition];
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if taicpu(hp).memoryordering<>[] then
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begin
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s:=s+'.';
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if moAq in taicpu(hp).memoryordering then s:=s+'aq';
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if moRl in taicpu(hp).memoryordering then s:=s+'rl';
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end;
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if taicpu(hp).ops<>0 then
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begin
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sep:=#9;
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for i:=0 to taicpu(hp).ops-1 do
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begin
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s:=s+sep+getopstr(owner.asminfo,taicpu(hp).oper[i]^);
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sep:=',';
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end;
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end;
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owner.writer.AsmWriteLn(s);
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end;
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{****************************************************************************}
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{ GNU RiscV Assembler writer }
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{****************************************************************************}
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constructor TRVGNUAssembler.CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean);
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begin
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inherited;
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InstrWriter := TRVInstrWriter.create(self);
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end;
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function TRVGNUAssembler.MakeCmdLine: TCmdStr;
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const
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arch_str: array[boolean,tcputype] of string[10] = (
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{$ifdef RISCV32}
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('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32ec'),
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('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32ecfd')
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{$endif RISCV32}
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{$ifdef RISCV64}
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('','rv64imac','rv64ima','rv64im','rv64i'),
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('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd')
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{$endif RISCV64}
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);
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begin
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result := inherited MakeCmdLine;
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Replace(result,'$ARCH',arch_str[current_settings.fputype=fpu_fd,current_settings.cputype]);
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{$ifdef RISCV32}
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case target_info.abi of
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abi_riscv_ilp32:
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Replace(result,'$ABI','ilp32');
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abi_riscv_ilp32f:
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Replace(result,'$ABI','ilp32f');
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else
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Replace(result,'$ABI','ilp32d');
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end;
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{$endif RISCV32}
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{$ifdef RISCV64}
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case target_info.abi of
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abi_riscv_lp64:
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Replace(result,'$ABI','lp64');
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abi_riscv_lp64f:
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Replace(result,'$ABI','lp64f');
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else
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Replace(result,'$ABI','lp64d');
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end;
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{$endif RISCV64}
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end;
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const
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as_riscv_gas_info : tasminfo =
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(
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id : as_gas;
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idtxt : 'AS';
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asmbin : 'as';
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asmcmd : '-o $OBJ $EXTRAOPT -march=$ARCH -mabi=$ABI $ASM';
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supported_targets : [system_riscv32_linux,system_riscv64_linux];
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flags : [af_needar,af_smartlink_sections,af_supports_dwarf];
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labelprefix : '.L';
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labelmaxlen : -1;
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comment : '# ';
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dollarsign: '$';
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);
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begin
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RegisterAssembler(as_riscv_gas_info,TRVGNUAssembler);
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end.
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