mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 06:28:06 +02:00
535 lines
16 KiB
ObjectPascal
535 lines
16 KiB
ObjectPascal
unit lpc8xx;
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{$goto on}
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{$define lpc8xx}
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interface
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{$PACKRECORDS 2}
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const
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//------------------------- Cortex-M0 Processor Exceptions Numbers -------------------------
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Reset_IRQn = -15; // 1 Reset Vector, invoked on Power up and warm reset
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NonMaskableInt_IRQn = -14; // 2 Non Maskable Interrupt
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HardFault_IRQn = -13; // 3 Cortex-M0 Hard Fault Interrupt
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SVCall_IRQn = -5; // 11 Cortex-M0 SV Call Interrupt
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PendSV_IRQn = -2; // 14 Cortex-M0 Pend SV Interrupt
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SysTick_IRQn = -1; // 15 Cortex-M0 System Tick Interrupt
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//------------------------- LPC8xx Specific Interrupt Numbers -------------------------
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SPI0_IRQn = 0; // SPI0
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SPI1_IRQn = 1; // SPI1
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UART0_IRQn = 3; // USART0
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UART1_IRQn = 4; // USART1
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UART2_IRQn = 5; // USART2
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I2C_IRQn = 8; // I2C
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SCT_IRQn = 9; // SCT
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MRT_IRQn = 10; // MRT
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CMP_IRQn = 11; // CMP
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WDT_IRQn = 12; // WDT
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BOD_IRQn = 13; // BOD
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WKT_IRQn = 15; // WKT Interrupt
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PININT0_IRQn = 24; // External Interrupt 0
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PININT1_IRQn = 25; // External Interrupt 1
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PININT2_IRQn = 26; // External Interrupt 2
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PININT3_IRQn = 27; // External Interrupt 3
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PININT4_IRQn = 28; // External Interrupt 4
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PININT5_IRQn = 29; // External Interrupt 5
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PININT6_IRQn = 30; // External Interrupt 6
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PININT7_IRQn = 31; // External Interrupt 7
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type
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{ ------------- System Control (SYSCON) ------------- }
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TSYSCON_Registers = record
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SYSMEMREMAP : longword;
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PRESETCTRL : longword;
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SYSPLLCTRL : longword;
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SYSPLLSTAT : longword;
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RESERVED0 : array [0 .. 3] of longword;
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SYSOSCCTRL : longword;
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WDTOSCCTRL : longword;
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RESERVED1 : array [0 .. 1] of longword;
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SYSRSTSTAT : longword;
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RESERVED2 : array [0 .. 2] of longword;
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SYSPLLCLKSEL : longword;
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SYSPLLCLKUEN : longword;
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RESERVED3 : array [0 .. 9] of longword;
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MAINCLKSEL : longword;
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MAINCLKUEN : longword;
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SYSAHBCLKDIV : longword;
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RESERVED4 : longword;
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SYSAHBCLKCTRL: longword;
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RESERVED5 : array [0 .. 3] of longword;
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UARTCLKDIV : longword;
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RESERVED6 : array [0 .. 17] of longword;
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CLKOUTSEL : longword;
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CLKOUTUEN : longword;
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CLKOUTDIV : longword;
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RESERVED7 : longword;
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UARTFRGDIV : longword;
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UARTFRGMULT : longword;
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RESERVED8 : longword;
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EXTTRACECMD : longword;
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PIOPORCAP0 : longword;
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RESERVED9 : array [0 .. 11] of longword;
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IOCONCLKDIV : array [0 .. 6] of longword;
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BODCTRL : longword;
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SYSTCKCAL : longword;
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RESERVED10 : array [0 .. 5] of longword;
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IRQLATENCY : longword;
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NMISRC : longword;
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PINTSEL : array [0 .. 7] of longword;
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RESERVED11 : array [0 .. 26] of longword;
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STARTERP0 : longword;
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RESERVED12 : array [0 .. 2] of longword;
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STARTERP1 : longword;
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RESERVED13 : array [0 .. 5] of longword;
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PDSLEEPCFG : longword;
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PDAWAKECFG : longword;
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PDRUNCFG : longword;
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RESERVED14 : array [0 .. 109] of longword;
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DEVICE_ID : longword;
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end;
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{ ------------- Pin Connect Block (IOCON) ------------- }
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TIOCON_Registers = record
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PIO0_17 : longword;
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PIO0_13 : longword;
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PIO0_12 : longword;
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PIO0_5 : longword;
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PIO0_4 : longword;
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PIO0_3 : longword;
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PIO0_2 : longword;
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PIO0_11 : longword;
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PIO0_10 : longword;
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PIO0_16 : longword;
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PIO0_15 : longword;
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PIO0_1 : longword;
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RESERVED0: longword;
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PIO0_9 : longword;
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PIO0_8 : longword;
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PIO0_7 : longword;
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PIO0_6 : longword;
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PIO0_0 : longword;
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PIO0_14 : longword;
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end;
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{ ------------- Flash Controller (FLASHCTRL) ------------- }
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TFLASHCTRL_Registers = record
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RESERVED0: array [0 .. 3] of longword;
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FLASHCFG : longword;
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RESERVED1: array [0 .. 2] of longword;
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FMSSTART : longword;
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FMSSTOP : longword;
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RESERVED2: longword;
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FMSW0 : longword;
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end;
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{ ------------- Power Management Unit (PMU) ------------- }
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TPMU_Registers = record
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PCON : longword;
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GPREG0 : longword;
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GPREG1 : longword;
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GPREG2 : longword;
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GPREG3 : longword;
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DPDCTRL: longword;
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end;
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{ ------------- Switch Matrix Register (SWM) ------------- }
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TSWM_Registers = record
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PINASSIGN : array [0 .. 8] of longword;
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RESERVED0 : array [0 .. 102] of longword;
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PINENABLE0: longword;
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end;
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{ ------------- General Purpose Input/Output (GPIO) ------------- }
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TGPIOPORT_Registers = record
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B0 : array [0 .. 17] of byte;
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RESERVED0: array [0 .. 2038] of word;
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W0 : array [0 .. 17] of longword;
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RESERVED1: array [0 .. 1005] of longword;
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DIR0 : longword;
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RESERVED2: array [0 .. 30] of longword;
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MASK0 : longword;
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RESERVED3: array [0 .. 30] of longword;
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PIN0 : longword;
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RESERVED4: array [0 .. 30] of longword;
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MPIN0 : longword;
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RESERVED5: array [0 .. 30] of longword;
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SET0 : longword;
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RESERVED6: array [0 .. 30] of longword;
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CLR0 : longword;
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RESERVED7: array [0 .. 30] of longword;
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NOT0 : longword;
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end;
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{ ------------- Pin interrupts/pattern match engine (PIN_INT) ------------- }
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TPININT_Registers = record
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ISEL : longword;
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IENR : longword;
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SIENR : longword;
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CIENR : longword;
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IENF : longword;
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SIENF : longword;
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CIENF : longword;
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RISE : longword;
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FALL : longword;
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IST : longword;
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PMCTRL: longword;
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PMSRC : longword;
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PMCFG : longword;
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end;
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{ ------------- CRC Engine (CRC) ------------- }
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TCRC_Registers = record
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MODE: longword;
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SEED: longword;
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SUM : longword;
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end;
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{ ------------- Comparator (CMP) ------------- }
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TCMP_Registers = record
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CTRL: longword;
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LAD : longword;
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end;
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{ ------------- Wakeup Timer (WKT) ------------- }
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TWKT_Registers = record
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CTRL : longword;
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RESERVED0: array [0 .. 1] of longword;
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COUNT : longword;
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end;
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{ ------------- Multi-Rate Timer(MRT) ------------- }
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TMRTChannel = record
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INTVAL: longword;
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TIMER : longword;
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CTRL : longword;
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STAT : longword;
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end;
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TMRT_Registers = record
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CHANNEL : array [0 .. 3] of TMRTChannel;
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RESERVED0: array [0 .. 0] of longword;
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IDLE_CH : longword;
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IRQ_FLAG : longword;
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end;
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{ ------------- Universal Asynchronous Receiver Transmitter (USART) ------------- }
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TUSART_Registers = record
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CFG : longword;
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CTRL : longword;
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STAT : longword;
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INTENSET : longword;
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INTENCLR : longword;
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RXDATA : longword;
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RXDATA_STAT: longword;
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TXDATA : longword;
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BRG : longword;
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INTSTAT : longword;
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end;
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{ ------------- Synchronous Serial Interface Controller (SPI) ------------- }
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TSPI_Registers = record
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CFG : longword;
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DLY : longword;
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STAT : longword;
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INTENSET: longword;
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INTENCLR: longword;
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RXDAT : longword;
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TXDATCTL: longword;
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TXDAT : longword;
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TXCTRL : longword;
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_DIV : longword;
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INTSTAT : longword;
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end;
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{ ------------- Inter-Integrated Circuit (I2C) ------------- }
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TI2C_Registers = record
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CFG : longword;
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STAT : longword;
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INTENSET : longword;
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INTENCLR : longword;
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TIMEOUT : longword;
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_DIV : longword;
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INTSTAT : longword;
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RESERVED0: longword;
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MSTCTL : longword;
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MSTTIME : longword;
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MSTDAT : longword;
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RESERVED1: array [0 .. 4] of longword;
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SLVCTL : longword;
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SLVDAT : longword;
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SLVADR0 : longword;
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SLVADR1 : longword;
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SLVADR2 : longword;
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SLVADR3 : longword;
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SLVQUAL0 : longword;
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RESERVED2: array [0 .. 8] of longword;
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MONRXDAT : longword;
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end;
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{ ------------- State Configurable Timer (SCT) ------------- }
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const
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CONFIG_SCT_nEV = 6;
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{ Number of match/compare registers }
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CONFIG_SCT_nRG = 5;
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{ Number of outputs }
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CONFIG_SCT_nOU = 4;
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type
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TSCTState = record
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STATE : longword;
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CTRL : longword;
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end;
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TSCTSet = record
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_SET : longword;
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CLR : longword;
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end;
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type
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TSCT_Registers = record
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CONFIG : longword;
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CTRL : longword;
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LIMIT : longword;
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HALT : longword;
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STOP : longword;
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START : longword;
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RESERVED1 : array [0 .. 9] of longword;
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COUNT : longword;
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STATE : longword;
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INPUT : longword;
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REGMODE : longword;
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OUTPUT : longword;
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OUTPUTDIRCTRL : longword;
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RES : longword;
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RESERVED2 : array [0 .. 36] of longword;
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EVEN : longword;
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EVFLAG : longword;
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CONEN : longword;
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CONFLAG : longword;
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MATCH_CAP : array [0 .. (CONFIG_SCT_nRG) - 1] of longword;
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RESERVED3 : array [0 .. (32 - CONFIG_SCT_nRG) - 1] of longword;
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MATCHREL_CAPCTRL: array [0 .. (CONFIG_SCT_nRG) - 1] of longword;
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RESERVED6 : array [0 .. (32 - CONFIG_SCT_nRG) - 1] of longword;
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EVENT : array [0 .. (CONFIG_SCT_nEV) - 1] of TSCTState;
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RESERVED9 : array [0 .. (128 - (2 * CONFIG_SCT_nEV)) - 1] of longword;
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_OUT : array [0 .. (CONFIG_SCT_nOU) - 1] of TSCTSet;
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end;
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{ ------------- Watchdog Timer (WDT) ------------- }
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TWDT_Registers = record
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_MOD : longword;
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TC : longword;
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FEED : longword;
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TV : longword;
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RESERVED0: longword;
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WARNINT : longword;
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WINDOW : longword;
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end;
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{ **************************************************************************** }
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{ Peripheral memory map }
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{ **************************************************************************** }
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const
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{ Base addresses }
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LPC_FLASH_BASE = $00000000;
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LPC_RAM_BASE = $10000000;
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LPC_ROM_BASE = $1FFF0000;
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LPC_APB0_BASE = $40000000;
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LPC_AHB_BASE = $50000000;
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{ APB0 peripherals }
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LPC_WDT_BASE = LPC_APB0_BASE + $00000;
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LPC_MRT_BASE = LPC_APB0_BASE + $04000;
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LPC_WKT_BASE = LPC_APB0_BASE + $08000;
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LPC_SWM_BASE = LPC_APB0_BASE + $0C000;
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LPC_PMU_BASE = LPC_APB0_BASE + $20000;
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LPC_CMP_BASE = LPC_APB0_BASE + $24000;
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LPC_FLASHCTRL_BASE = LPC_APB0_BASE + $40000;
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LPC_IOCON_BASE = LPC_APB0_BASE + $44000;
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LPC_SYSCON_BASE = LPC_APB0_BASE + $48000;
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LPC_I2C_BASE = LPC_APB0_BASE + $50000;
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LPC_SPI0_BASE = LPC_APB0_BASE + $58000;
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LPC_SPI1_BASE = LPC_APB0_BASE + $5C000;
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LPC_USART0_BASE = LPC_APB0_BASE + $64000;
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LPC_USART1_BASE = LPC_APB0_BASE + $68000;
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LPC_USART2_BASE = LPC_APB0_BASE + $6C000;
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{ AHB peripherals }
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LPC_CRC_BASE = LPC_AHB_BASE + $00000;
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LPC_SCT_BASE = LPC_AHB_BASE + $04000;
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LPC_GPIO_PORT_BASE = $A0000000;
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LPC_PIN_INT_BASE = LPC_GPIO_PORT_BASE + $4000;
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// ****************************************************************************
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// Peripheral declaration
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// ****************************************************************************
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{$ALIGN 2}
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var
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WDT : TWDT_Registers absolute LPC_WDT_BASE;
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MRT : TMRT_Registers absolute LPC_MRT_BASE;
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WKT : TWKT_Registers absolute LPC_WKT_BASE;
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SWM : TSWM_Registers absolute LPC_SWM_BASE;
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PMU : TPMU_Registers absolute LPC_PMU_BASE;
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CMP : TCMP_Registers absolute LPC_CMP_BASE;
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FLASHCTRL: TFLASHCTRL_Registers absolute LPC_FLASHCTRL_BASE;
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IOCON : TIOCON_Registers absolute LPC_IOCON_BASE;
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SYSCON : TSysCon_Registers absolute LPC_SYSCON_BASE;
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I2C : TI2C_Registers absolute LPC_I2C_BASE;
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SPI0 : TSPI_Registers absolute LPC_SPI0_BASE;
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SPI1 : TSPI_Registers absolute LPC_SPI1_BASE;
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USART0 : TUSART_Registers absolute LPC_USART0_BASE;
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USART1 : TUSART_Registers absolute LPC_USART0_BASE;
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USART2 : TUSART_Registers absolute LPC_USART0_BASE;
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CRC : TCRC_Registers absolute LPC_CRC_BASE;
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SCT : TSCT_Registers absolute LPC_SCT_BASE;
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GPIO_PORT: TGPIOPort_Registers absolute LPC_GPIO_PORT_BASE;
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PIN_INT : TPININT_Registers absolute LPC_PIN_INT_BASE;
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implementation
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procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
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procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
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procedure Startup_Checksum; external name 'Startup_Checksum';
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procedure SVCall_interrupt; external name 'SVCall_interrupt';
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procedure PendSV_interrupt; external name 'PendSV_interrupt';
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procedure SysTick_interrupt; external name 'SysTick_interrupt';
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procedure SPI0_Interrupt; external name 'SPI0_Interrupt';
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procedure SPI1_Interrupt; external name 'SPI1_Interrupt';
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procedure UART0_Interrupt; external name 'UART0_Interrupt';
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procedure UART1_Interrupt; external name 'UART1_Interrupt';
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procedure UART2_Interrupt; external name 'UART2_Interrupt';
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procedure I2C_Interrupt; external name 'I2C_Interrupt';
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procedure SCT_Interrupt; external name 'SCT_Interrupt';
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procedure MRT_Interrupt; external name 'MRT_Interrupt';
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procedure CMP_Interrupt; external name 'CMP_Interrupt';
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procedure WDT_Interrupt; external name 'WDT_Interrupt';
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procedure BOD_Interrupt; external name 'BOD_Interrupt';
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procedure WKT_Interrupt; external name 'WKT_Interrupt';
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procedure PINIT0_Interrupt; external name 'PINIT0_Interrupt';
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procedure PINIT1_Interrupt; external name 'PINIT1_Interrupt';
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procedure PINIT2_Interrupt; external name 'PINIT2_Interrupt';
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procedure PINIT3_Interrupt; external name 'PINIT3_Interrupt';
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procedure PINIT4_Interrupt; external name 'PINIT4_Interrupt';
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procedure PINIT5_Interrupt; external name 'PINIT5_Interrupt';
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procedure PINIT6_Interrupt; external name 'PINIT6_Interrupt';
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procedure PINIT7_Interrupt; external name 'PINIT7_Interrupt';
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{$I cortexm0_start.inc}
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procedure Vectors; assembler;
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nostackframe;
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label interrupt_vectors;
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asm
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.section ".init.interrupt_vectors"
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interrupt_vectors:
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.long _stack_top
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.long Startup
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.long NonMaskableInt_interrupt
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.long Hardfault_interrupt
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.long 0
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.long 0
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.long 0
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.long Startup_Checksum
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.long 0
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.long 0
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.long 0
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.long SVCall_interrupt
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.long 0
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.long 0
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.long PendSV_interrupt
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.long SysTick_interrupt
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.long SPI0_Interrupt
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.long SPI1_Interrupt
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.long 0
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.long UART0_Interrupt
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.long UART1_Interrupt
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.long UART2_Interrupt
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.long 0
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.long 0
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.long I2C_Interrupt
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.long SCT_Interrupt
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.long MRT_Interrupt
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.long CMP_Interrupt
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.long WDT_Interrupt
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.long BOD_Interrupt
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.long 0
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.long WKT_Interrupt
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long PINIT0_Interrupt
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.long PINIT1_Interrupt
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.long PINIT2_Interrupt
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.long PINIT3_Interrupt
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.long PINIT4_Interrupt
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.long PINIT5_Interrupt
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.long PINIT6_Interrupt
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.long PINIT7_Interrupt
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.weak NonMaskableInt_interrupt
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.weak Hardfault_interrupt
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.weak Startup_Checksum
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.weak SVCall_interrupt
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.weak PendSV_interrupt
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.weak SysTick_interrupt
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.weak SPI0_Interrupt
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.weak SPI1_Interrupt
|
|
.weak UART0_Interrupt
|
|
.weak UART1_Interrupt
|
|
.weak UART2_Interrupt
|
|
.weak I2C_Interrupt
|
|
.weak SCT_Interrupt
|
|
.weak MRT_Interrupt
|
|
.weak CMP_Interrupt
|
|
.weak WDT_Interrupt
|
|
.weak BOD_Interrupt
|
|
.weak WKT_Interrupt
|
|
.weak PINIT0_Interrupt
|
|
.weak PINIT1_Interrupt
|
|
.weak PINIT2_Interrupt
|
|
.weak PINIT3_Interrupt
|
|
.weak PINIT4_Interrupt
|
|
.weak PINIT5_Interrupt
|
|
.weak PINIT6_Interrupt
|
|
.weak PINIT7_Interrupt
|
|
|
|
.set NonMaskableInt_interrupt, Startup
|
|
.set Hardfault_interrupt , Startup
|
|
.set SVCall_interrupt , Startup
|
|
.set PendSV_interrupt , Startup
|
|
.set SysTick_interrupt , Startup
|
|
|
|
.set SPI0_Interrupt , Startup
|
|
.set SPI1_Interrupt , Startup
|
|
.set UART0_Interrupt , Startup
|
|
.set UART1_Interrupt , Startup
|
|
.set UART2_Interrupt , Startup
|
|
.set I2C_Interrupt , Startup
|
|
.set SCT_Interrupt , Startup
|
|
.set MRT_Interrupt , Startup
|
|
.set CMP_Interrupt , Startup
|
|
.set WDT_Interrupt , Startup
|
|
.set BOD_Interrupt , Startup
|
|
.set WKT_Interrupt , Startup
|
|
.set PINIT0_Interrupt, Startup
|
|
.set PINIT1_Interrupt, Startup
|
|
.set PINIT2_Interrupt, Startup
|
|
.set PINIT3_Interrupt, Startup
|
|
.set PINIT4_Interrupt, Startup
|
|
.set PINIT5_Interrupt, Startup
|
|
.set PINIT6_Interrupt, Startup
|
|
.set PINIT7_Interrupt, Startup
|
|
|
|
.text
|
|
end;
|
|
|
|
end.
|