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aoptcpu.pas
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* factored out TX86AsmOptimizer.OptPass2Imul
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2017-01-06 22:25:24 +00:00 |
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aoptcpub.pas
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aoptcpud.pas
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cgcpu.pas
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+ implemented OP_SHR/OP_SHL/OP_SAR in i386's tcg64f386.a_op64_reg_ref
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2017-04-18 14:34:20 +00:00 |
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cpubase.inc
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cpuelf.pas
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cpuinfo.pas
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+ added 486 to the list of supported CPUs on the i8086 and i386 targets
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2016-03-23 15:07:56 +00:00 |
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cpunode.pas
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cpupara.pas
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* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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2017-02-25 11:46:35 +00:00 |
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cpupi.pas
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* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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2016-12-16 22:41:21 +00:00 |
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cputarg.pas
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hlcgcpu.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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i386att.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386atts.inc
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* x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:
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2016-11-21 02:07:13 +00:00 |
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i386int.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386nop.inc
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* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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2016-11-21 13:59:44 +00:00 |
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i386op.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386prop.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386tab.inc
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* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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2016-11-21 13:59:44 +00:00 |
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n386add.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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n386cal.pas
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syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed
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2016-12-02 09:29:09 +00:00 |
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n386flw.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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n386inl.pas
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+ i386: generate optimized code for 64-bit arithmetic shifts by constant amount. Shifts by 63 and by less than 32 take just two instructions, shifts by 32..62 bits are done with 3 instructions.
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2013-10-29 16:10:13 +00:00 |
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n386ld.pas
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* factored out the loading of threadvars in its own method, and put the
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2015-09-12 23:32:53 +00:00 |
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n386mat.pas
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* avoid the AND instruction in the i386 shr64/shl64 code, by using TEST+JZ,
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2017-04-18 11:36:48 +00:00 |
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n386mem.pas
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n386set.pas
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r386ari.inc
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r386att.inc
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r386con.inc
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* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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2013-10-03 08:08:04 +00:00 |
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r386dwrf.inc
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r386int.inc
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r386iri.inc
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r386nasm.inc
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r386nor.inc
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r386nri.inc
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r386num.inc
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* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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2013-10-03 08:08:04 +00:00 |
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r386ot.inc
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r386rni.inc
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r386sri.inc
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r386stab.inc
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* merged avx support in inline assembler developed by Torsten Grundke
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2012-10-06 19:47:18 +00:00 |
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r386std.inc
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ra386att.pas
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ra386int.pas
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rgcpu.pas
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symcpu.pas
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