fpc/compiler/riscv
Jonas Maebe 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint,
so it also works for 32 bit targets and a high level code generator
    (where aint is still 32 bit, but 64 bit operations are not decomposed)

git-svn-id: trunk@41441 -
2019-02-24 19:58:37 +00:00
..
aasmcpu.pas * fixed compilation with -O3 (one false positive, one real error) 2018-11-01 20:39:38 +00:00
agrvgas.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
cgrv.pas Fix compilation with -dEXTDEBUG 2018-10-13 11:34:53 +00:00
hlcgrv.pas
nrvadd.pas Fix riscv32 compilation error introduced in last commit 2018-11-16 10:24:27 +00:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
nrvset.pas * let all the case code generation work with tconstexprint instead of aint, 2019-02-24 19:58:37 +00:00
rgcpu.pas Fix bug in lui+addi immediate load for spilling code. 2018-09-16 20:51:15 +00:00