nickysn 0f010430cc + better precision in determining the registers, read by mul/imul/div/idiv in ... i386's TCpuAsmOptimizer.RegReadByInstruction: * mul doesn't read edx (unless included in operand) * 8-bit mul and imul don't read ah (unless included in operand) * 8-bit div and idiv don't read edx (unless included in operand) git-svn-id: trunk@35958 -		2017-04-26 16:17:31 +00:00
..
aoptcpu.pas	+ better precision in determining the registers, read by mul/imul/div/idiv in	2017-04-26 16:17:31 +00:00
aoptcpub.pas	* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same	2016-04-21 20:14:01 +00:00
aoptcpud.pas	* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same	2016-04-21 20:14:01 +00:00
cgcpu.pas	* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr	2017-04-19 21:30:31 +00:00
cpubase.inc
cpuelf.pas
cpuinfo.pas
cpunode.pas	* automatically generate necessary indirect symbols when a new assembler	2016-07-20 20:53:03 +00:00
cpupara.pas	* use pocalls_cdecl and cstylearrayofconst more consistently instead of	2017-02-25 11:46:35 +00:00
cpupi.pas	* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can	2016-12-16 22:41:21 +00:00
cputarg.pas
hlcgcpu.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
i386att.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386atts.inc	* x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:	2016-11-21 02:07:13 +00:00
i386int.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386nop.inc	* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.	2016-11-21 13:59:44 +00:00
i386op.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386prop.inc	* proper register change info for the movs,cmps and scas x86 string instructions	2017-04-23 21:30:25 +00:00
i386tab.inc	* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.	2016-11-21 13:59:44 +00:00
n386add.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
n386cal.pas	syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed	2016-12-02 09:29:09 +00:00
n386flw.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
n386inl.pas
n386ld.pas
n386mat.pas	* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr	2017-04-19 21:30:31 +00:00
n386mem.pas
n386set.pas
r386ari.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386att.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386con.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386dwrf.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386int.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386iri.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386nasm.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386nor.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386nri.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386num.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386ot.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386rni.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386sri.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386stab.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
r386std.inc	+ added individual bits of the x86 flags register as subregisters	2017-04-26 13:52:52 +00:00
ra386att.pas
ra386int.pas
rgcpu.pas
symcpu.pas