fpc/compiler/riscv
Jonas Maebe 4cd6f59bc3 * changed create_hlcodegen into a procvar, so that we don't have to insert
hlcgllvm in the uses clause of every unit that calls create_hlcodegen
   o prevents dependency cycles that can cause llvm codegen units to init
     before the cpu variants, which is bad since the llvm versions have to
     override the cpu variants in their init code (+ added checks in the
     init code that they are in fact initialised later)

git-svn-id: branches/debug_eh@40410 -
2018-11-29 21:31:15 +00:00
..
aasmcpu.pas * fixed compilation with -O3 (one false positive, one real error) 2018-11-01 20:39:38 +00:00
agrvgas.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
cgrv.pas Fix compilation with -dEXTDEBUG 2018-10-13 11:34:53 +00:00
hlcgrv.pas * changed create_hlcodegen into a procvar, so that we don't have to insert 2018-11-29 21:31:15 +00:00
nrvadd.pas Fix riscv32 compilation error introduced in last commit 2018-11-16 10:24:27 +00:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
nrvset.pas Add RV64GC cpu type. 2018-07-21 22:34:42 +00:00
rgcpu.pas Fix bug in lui+addi immediate load for spilling code. 2018-09-16 20:51:15 +00:00