florian 5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, ... this is an exact operation so it is always allowed * change only divisions by normal numbers into multiplications git-svn-id: trunk@29085 -		2014-11-16 20:47:38 +00:00
..
aopt386.pas	* support disabling the i386 peephole optimizer with -Oonopeephole	2014-02-05 00:27:16 +00:00
cgcpu.pas	- moved deallocation of NR_PIC_OFFSET_REG from the x86_64 to the i386 code	2014-10-25 17:47:44 +00:00
cpubase.inc	* optimize mov/lea	2013-11-01 19:01:14 +00:00
cpuelf.pas	AROS: assembler fixes	2014-08-18 11:25:55 +00:00
cpuinfo.pas	+ change always floating point divisions into multiplications if they are a power of two,	2014-11-16 20:47:38 +00:00
cpunode.pas	* isolated segment-related functionality of tabsolutevarsym into i386/i8086-	2014-03-30 15:42:53 +00:00
cpupara.pas	* fix working with short record function results under OS/2	2014-10-20 15:40:17 +00:00
cpupi.pas
cputarg.pas	merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run.	2014-08-17 18:18:07 +00:00
csopt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
daopt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
hlcgcpu.pas	+ added method reference_reset_base with support for different pointer types to	2014-03-28 00:01:18 +00:00
i386att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386atts.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386nop.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
i386op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386prop.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386tab.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
n386add.pas	* fix warnings when compiling the compiler with DFA optimizer enabled on i386	2014-08-20 12:28:44 +00:00
n386cal.pas	AROS: syscall (library call) support for based on the Amiga/68k and MorphOS/PPC versions	2014-08-19 00:39:18 +00:00
n386flw.pas	* Provide initialization of all variables, fixes cycling with OPT="-dTEST_WIN32_SEH -OoDFA".	2014-09-08 18:08:12 +00:00
n386inl.pas	+ i386: generate optimized code for 64-bit arithmetic shifts by constant amount. Shifts by 63 and by less than 32 take just two instructions, shifts by 32..62 bits are done with 3 instructions.	2013-10-29 16:10:13 +00:00
n386ld.pas	* isolated segment-related functionality of tabsolutevarsym into i386/i8086-	2014-03-30 15:42:53 +00:00
n386mat.pas	* i386: switch the div/mod node to shared code, leaving in place the specific optimization for division by power of 2.	2014-06-15 16:20:53 +00:00
n386mem.pas	* moved x86-specific tpointerdef functionality to architecture-specific	2014-03-30 21:04:36 +00:00
n386set.pas	* cleanup of unused units	2013-07-07 20:00:33 +00:00
popt386.pas	* i386: For integer comparisons with zero, emit "test $-1,%reg" instead of "test %reg,%reg". It is more spilling-friendly, because it transforms into "test $-1,spilltemp" and does not require a register.	2014-04-20 19:16:58 +00:00
r386ari.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386att.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386con.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386dwrf.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386int.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386iri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386nasm.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386nor.inc
r386nri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386num.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386ot.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386rni.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386sri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386stab.inc
r386std.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
ra386att.pas
ra386int.pas
rgcpu.pas
rropt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
symcpu.pas	Add new procedure option: po_syscall_has_libsym,	2014-10-03 19:26:16 +00:00