florian 32e17c5114 * for avr1, do not save registers during an interrupt procedure, as it has no memory to store them ... git-svn-id: trunk@44139 - (cherry picked from commit 2135b9b724) # Conflicts: # compiler/msg/errore.msg # compiler/msgidx.inc # compiler/msgtxt.inc		2021-10-24 12:40:37 +02:00
..
aasmcpu.pas	* for avr1, do not save registers during an interrupt procedure, as it has no memory to store them	2021-10-24 12:40:37 +02:00
agavrgas.pas	* LDD/STD need always an offset, resolves #33086	2018-01-28 21:06:13 +00:00
aoptcpu.pas	* based on a patch by Christo Crause: more compiler fixes for avrtiny, resolves #36646	2021-10-24 12:40:37 +02:00
aoptcpub.pas	Added some peephole optimizations, and fixed generic unconditional jump optimizations, for AVR.	2015-06-13 12:25:11 +00:00
aoptcpud.pas
avrreg.dat	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ccpuinnr.inc	- Adds intrinsics to save/restore SREG when disabling interrupts.	2021-10-24 12:40:36 +02:00
cgcpu.pas	* for avr1, do not save registers during an interrupt procedure, as it has no memory to store them	2021-10-24 12:40:37 +02:00
cpubase.pas	+ AVR: GetDefaultZeroReg and GetDefaultTmpReg	2021-10-24 12:40:37 +02:00
cpuinfo.pas	* patch by Christo Crause: more avr1 controllers and remove attiny28 from avr25 makefile list, resolves #36686	2021-10-24 12:40:37 +02:00
cpunode.pas	+ implemented some AVR specific intrinsics	2017-11-01 16:33:34 +00:00
cpupara.pas	+ AVR: initial support for the avrtiny architecture	2021-10-24 12:40:37 +02:00
cpupi.pas	* AVR: decide after compiler if a certain subroutine is suitable for avr1, if not, replace it by sleep and warn	2021-10-24 12:40:37 +02:00
cputarg.pas
hlcgcpu.pas
itcpugas.pas	+ xch instruction for avr	2016-11-19 19:21:09 +00:00
navradd.pas	+ AVR: GetDefaultZeroReg and GetDefaultTmpReg	2021-10-24 12:40:37 +02:00
navrcnv.pas
navrinl.pas	AVR: Add optimizations for sign testing, and a better Abs() implementation.	2021-10-24 12:40:36 +02:00
navrmat.pas	* AVR: use CP ...,r1 instead of CPI ...,0 to enable all registers being used as first operand	2021-10-24 12:40:37 +02:00
navrmem.pas	* use unique internalerror instead of copying that from ncgmem (though it should never happen that both occur at once in a AVR compiler)	2017-07-28 15:54:03 +00:00
navrutil.pas	* rework InsertInitFinalTable a bit more so that the list of init/fini entries does not need to be generated twice for AVR	2017-05-23 19:58:39 +00:00
raavr.pas	* max_operands needs only to be 2 on avr	2021-10-24 12:40:36 +02:00
raavrgas.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
ravrcon.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrdwa.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrnor.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrnum.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrrni.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsri.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsta.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrstd.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsup.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
rgcpu.pas	+ AVR: initial support for the avrtiny architecture	2021-10-24 12:40:37 +02:00
symcpu.pas	o fixes handling of iso i/o parameters/program parameters:	2015-05-01 20:58:31 +00:00
tripletcpu.pas	* merged macOS/AArch64 support + revisions these changes depended on	2020-09-15 19:40:36 +00:00