Károly Balogh 4431ba2c08 merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run. ... git-svn-id: trunk@28432 -		2014-08-17 18:18:07 +00:00
..
aopt386.pas
cgcpu.pas
cpubase.inc
cpuelf.pas
cpuinfo.pas
cpunode.pas
cpupara.pas
cpupi.pas
cputarg.pas	merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run.	2014-08-17 18:18:07 +00:00
csopt386.pas
daopt386.pas
hlcgcpu.pas
i386att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386atts.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386nop.inc
i386op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386prop.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386tab.inc
n386add.pas	* i386: improvements to 64-bit comparison code, also serves as a good base for m68k target:	2014-07-25 13:21:44 +00:00
n386cal.pas
n386flw.pas
n386inl.pas
n386ld.pas
n386mat.pas	* i386: switch the div/mod node to shared code, leaving in place the specific optimization for division by power of 2.	2014-06-15 16:20:53 +00:00
n386mem.pas
n386set.pas
popt386.pas
r386ari.inc
r386att.inc
r386con.inc
r386dwrf.inc
r386int.inc
r386iri.inc
r386nasm.inc
r386nor.inc
r386nri.inc
r386num.inc
r386ot.inc
r386rni.inc
r386sri.inc
r386stab.inc
r386std.inc
ra386att.pas
ra386int.pas
rgcpu.pas
rropt386.pas
symcpu.pas	* reimplemented r28329 in a different way, as suggested by Jonas	2014-08-07 19:36:52 +00:00