florian c7290bfb78 * enclose {$define DEBUG_AOPTCPU} in {$ifdef EXTDEBUG}		2025-03-10 22:50:49 +01:00
..
aoptcpu.pas	* enclose {$define DEBUG_AOPTCPU} in {$ifdef EXTDEBUG}	2025-03-10 22:50:49 +01:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	+ more sext.b usage	2025-02-25 22:50:14 +01:00
cpuinfo.pas	+ RV64GCB CPU type	2025-02-20 22:41:35 +01:00
cpunode.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
cpupara.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nrv64add.pas	+ RiscV: support ZMMUL extension	2025-01-26 14:43:57 +01:00
nrv64cal.pas
nrv64cnv.pas
nrv64ld.pas
nrv64mat.pas	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
rrv64con.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64dwa.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64nor.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64num.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64rni.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sri.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sta.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64std.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sup.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
symcpu.pas
tripletcpu.pas