Jonas Maebe 4c68ea1000 * use pocalls_cdecl and cstylearrayofconst more consistently instead of ... ad hoc set constants containing varying number cdecl-like calling conventions o added pocall_sysv_abi_cdecl and pocall_ms_abi_cdecl to cstylearrayofconst o also allow C-style blocks with mwpascal instead of cdecl (mwpascal = cdecl with "const" = "constref" for record parameters) o did not touch cases related to name mangling and import/export names, because those are a real mess and easily break things left and right :/ git-svn-id: trunk@35479 -		2017-02-25 11:46:35 +00:00
..
aoptcpu.pas	* factored out TX86AsmOptimizer.OptPass2Imul	2017-01-06 22:25:24 +00:00
aoptcpub.pas	* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same	2016-04-21 20:14:01 +00:00
aoptcpud.pas	* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same	2016-04-21 20:14:01 +00:00
cgcpu.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
cpubase.inc
cpuelf.pas
cpuinfo.pas	+ added 486 to the list of supported CPUs on the i8086 and i386 targets	2016-03-23 15:07:56 +00:00
cpunode.pas	* automatically generate necessary indirect symbols when a new assembler	2016-07-20 20:53:03 +00:00
cpupara.pas	* use pocalls_cdecl and cstylearrayofconst more consistently instead of	2017-02-25 11:46:35 +00:00
cpupi.pas	* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can	2016-12-16 22:41:21 +00:00
cputarg.pas
hlcgcpu.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
i386att.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386atts.inc	* x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:	2016-11-21 02:07:13 +00:00
i386int.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386nop.inc	* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.	2016-11-21 13:59:44 +00:00
i386op.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386prop.inc	+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933	2016-11-18 20:19:39 +00:00
i386tab.inc	* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.	2016-11-21 13:59:44 +00:00
n386add.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
n386cal.pas	syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed	2016-12-02 09:29:09 +00:00
n386flw.pas	+ added volatility information to all memory references	2016-11-27 18:17:37 +00:00
n386inl.pas
n386ld.pas	* factored out the loading of threadvars in its own method, and put the	2015-09-12 23:32:53 +00:00
n386mat.pas
n386mem.pas
n386set.pas
r386ari.inc
r386att.inc
r386con.inc
r386dwrf.inc
r386int.inc
r386iri.inc
r386nasm.inc
r386nor.inc
r386nri.inc
r386num.inc
r386ot.inc
r386rni.inc
r386sri.inc
r386stab.inc
r386std.inc
ra386att.pas
ra386int.pas
rgcpu.pas
symcpu.pas