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aasmcpu.pas
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* MIPS: reworked and fixed procedure fixup_jmps:
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2016-02-12 13:53:04 +00:00 |
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aoptcpu.pas
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* MIPS: fixed TCpuAsmOptimizer.InstructionLoadsFromReg, it now correctly considers instructions that read their first operand.
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2017-04-23 15:26:17 +00:00 |
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aoptcpub.pas
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aoptcpud.pas
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cgcpu.pas
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* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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2016-12-16 22:41:21 +00:00 |
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cpubase.pas
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* cpubase unit, function findreg_by_number and dwarf_reg:
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2016-11-06 18:04:50 +00:00 |
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cpuelf.pas
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* MIPS: some progress with linker:
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2016-03-13 17:13:23 +00:00 |
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cpugas.pas
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* restructured the the TExternalAssembler constructors so that the
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2016-11-09 19:51:20 +00:00 |
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cpuinfo.pas
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- removed unused constants
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2017-03-26 13:06:34 +00:00 |
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cpunode.pas
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* automatically generate necessary indirect symbols when a new assembler
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2016-07-20 20:53:03 +00:00 |
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cpupara.pas
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* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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2016-12-16 22:41:21 +00:00 |
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cpupi.pas
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* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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2016-12-16 22:41:21 +00:00 |
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cputarg.pas
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hlcgcpu.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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itcpugas.pas
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* Removed unused vars for mipsel compiler.
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2015-09-17 15:46:30 +00:00 |
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mipsreg.dat
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Fix stabs number for FPU register, which start at 38 instead of 32
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2016-11-06 18:01:08 +00:00 |
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ncpuadd.pas
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* Removed unused vars for mipsel compiler.
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2015-09-17 15:46:30 +00:00 |
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ncpucall.pas
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* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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2017-02-25 11:46:35 +00:00 |
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ncpucnv.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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ncpuinln.pas
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ncpuld.pas
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ncpumat.pas
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* synchronised with r28168 of trunk
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2014-07-05 21:30:28 +00:00 |
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ncpuset.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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opcode.inc
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+ MIPS: added movn and movz instructions.
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2014-06-19 22:44:17 +00:00 |
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racpugas.pas
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* reverted r35424, wasn't ready for commit yet
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2017-02-11 21:21:44 +00:00 |
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rgcpu.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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rmipscon.inc
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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rmipsdwf.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgas.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgri.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgss.inc
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rmipsnor.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsnum.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsrni.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssri.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssta.inc
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Regenerated after change in mipsreg.dat
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2016-11-06 18:01:52 +00:00 |
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rmipsstd.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssup.inc
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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strinst.inc
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+ MIPS: added movn and movz instructions.
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2014-06-19 22:44:17 +00:00 |
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symcpu.pas
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o fixes handling of iso i/o parameters/program parameters:
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2015-05-01 20:58:31 +00:00 |
