sergei 5356f17fa5 * i386: switch the div/mod node to shared code, leaving in place the specific optimization for division by power of 2. ... git-svn-id: trunk@27975 -		2014-06-15 16:20:53 +00:00
..
aopt386.pas	* support disabling the i386 peephole optimizer with -Oonopeephole	2014-02-05 00:27:16 +00:00
cgcpu.pas	* i386: push references with size OS_F64 using less instructions.	2014-03-27 14:48:23 +00:00
cpubase.inc	* optimize mov/lea	2013-11-01 19:01:14 +00:00
cpuelf.pas	+ Support GOT/gp-relative constants in GAS and internal assemblers, MIPS and i386.	2014-02-26 14:54:47 +00:00
cpuinfo.pas	+ support for FMA intrinsic: if there is no hardware support, the compiler throws an error.	2014-04-13 19:21:54 +00:00
cpunode.pas	* isolated segment-related functionality of tabsolutevarsym into i386/i8086-	2014-03-30 15:42:53 +00:00
cpupara.pas	- i386, x86_64, SPARC: removed paramanager.getintparaloc overrides, it is handled by generic implementation since r24716.	2014-02-24 16:01:14 +00:00
cpupi.pas	* removed systems_need_16_byte_stack_alignment and use target_info.stackalign instead	2012-09-02 14:32:21 +00:00
cputarg.pas	* Sync with trunk r23404.	2013-01-16 13:21:51 +00:00
csopt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
daopt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
hlcgcpu.pas	+ added method reference_reset_base with support for different pointer types to	2014-03-28 00:01:18 +00:00
i386att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386atts.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386nop.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
i386op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386prop.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i386tab.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
n386add.pas	+ i386: inline 64-bit multiplications if overflow checking is disabled and not optimizing for size. Rough testing on Core 2 Duo shows speed improvement by factor of 5, even despite inlined code does not check for zero upper dwords.	2014-01-18 11:41:55 +00:00
n386cal.pas	Add -Caoldwin32gnu ABI option to cope with 'ret $4' issues in old GNU mingw32 C compiler (version below 4.7)	2014-01-20 22:47:46 +00:00
n386flw.pas	* fixed setting of pi_uses_exception flags and unified usage, they should be set in pass_1	2014-02-08 14:59:07 +00:00
n386inl.pas	+ i386: generate optimized code for 64-bit arithmetic shifts by constant amount. Shifts by 63 and by less than 32 take just two instructions, shifts by 32..62 bits are done with 3 instructions.	2013-10-29 16:10:13 +00:00
n386ld.pas	* isolated segment-related functionality of tabsolutevarsym into i386/i8086-	2014-03-30 15:42:53 +00:00
n386mat.pas	* i386: switch the div/mod node to shared code, leaving in place the specific optimization for division by power of 2.	2014-06-15 16:20:53 +00:00
n386mem.pas	* moved x86-specific tpointerdef functionality to architecture-specific	2014-03-30 21:04:36 +00:00
n386set.pas	* cleanup of unused units	2013-07-07 20:00:33 +00:00
popt386.pas	* i386: For integer comparisons with zero, emit "test $-1,%reg" instead of "test %reg,%reg". It is more spilling-friendly, because it transforms into "test $-1,spilltemp" and does not require a register.	2014-04-20 19:16:58 +00:00
r386ari.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386att.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386con.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386dwrf.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386int.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386iri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386nasm.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386nor.inc	* merged avx support in inline assembler developed by Torsten Grundke	2012-10-06 19:47:18 +00:00
r386nri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386num.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386ot.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386rni.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386sri.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
r386stab.inc	* merged avx support in inline assembler developed by Torsten Grundke	2012-10-06 19:47:18 +00:00
r386std.inc	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00
ra386att.pas
ra386int.pas
rgcpu.pas
rropt386.pas	* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables	2013-12-01 17:02:08 +00:00
symcpu.pas	* forgot to commit the changes to i386/symcpu.pas in r27549	2014-04-13 18:44:35 +00:00