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aasmcpu.pas
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aoptcpu.pas
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* MIPS, TCpuAsmOptimizer.GetNextInstructionUsingReg: test that returned item is actually an instruction, because GetNextInstruction can sometimes stop on labels.
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2014-08-10 21:31:13 +00:00 |
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aoptcpub.pas
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aoptcpud.pas
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cgcpu.pas
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- MIPS: removed allocation of stack/frame pointer registers in prologue, hacks like this are no longer needed since r27104.
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2014-08-21 19:36:00 +00:00 |
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cpubase.pas
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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cpuelf.pas
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* fixed DFA warnings for MIPS and AVR
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2014-08-20 15:05:43 +00:00 |
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cpugas.pas
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cpuinfo.pas
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cpunode.pas
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cpupara.pas
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cpupi.pas
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cputarg.pas
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hlcgcpu.pas
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itcpugas.pas
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mipsreg.dat
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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ncpuadd.pas
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ncpucall.pas
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ncpucnv.pas
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* MIPS: optimized conversion of unsigned 32-bit integers to float, now uses one integer register instead of two and does not generate redundant move.
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2014-08-27 21:23:47 +00:00 |
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ncpuinln.pas
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ncpuld.pas
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ncpumat.pas
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ncpuset.pas
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opcode.inc
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+ MIPS: added movn and movz instructions.
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2014-06-19 22:44:17 +00:00 |
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racpugas.pas
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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rgcpu.pas
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- MIPS: completely removed trgcpu.add_constraints method.
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2014-06-19 03:59:24 +00:00 |
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rmipscon.inc
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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rmipsdwf.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgas.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgri.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsgss.inc
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rmipsnor.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsnum.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsrni.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssri.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssta.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipsstd.inc
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* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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2014-06-17 23:15:34 +00:00 |
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rmipssup.inc
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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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2014-06-22 22:01:44 +00:00 |
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strinst.inc
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+ MIPS: added movn and movz instructions.
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2014-06-19 22:44:17 +00:00 |
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symcpu.pas
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