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https://gitlab.com/freepascal.org/fpc/source.git
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126 lines
3.7 KiB
ObjectPascal
126 lines
3.7 KiB
ObjectPascal
unit ATtiny28;
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{$goto on}
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interface
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var
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// PORTD
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PORTD : byte absolute $00+$32; // Port D Data Register
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DDRD : byte absolute $00+$31; // Port D Data Direction Register
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PIND : byte absolute $00+$30; // Port D Input Pins
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// CPU
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SREG : byte absolute $00+$3F; // Status Register
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ICR : byte absolute $00+$26; // Interrupt Control Register
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MCUCS : byte absolute $00+$27; // MCU Control and Status Register
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OSCCAL : byte absolute $00+$20; // Status Register
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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// TIMER_COUNTER_0
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IFR : byte absolute $00+$25; // Interrupt Flag register
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TCCR0 : byte absolute $00+$24; // Timer/Counter0 Control Register
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TCNT0 : byte absolute $00+$23; // Timer Counter 0
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// WATCHDOG
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WDTCR : byte absolute $00+$21; // Watchdog Timer Control Register
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// EXTERNAL_INTERRUPT
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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PACR : byte absolute $00+$3A; // Port A Control Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// PORTB
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PINB : byte absolute $00+$36; // Port B Input Pins
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// MODULATOR
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MODCR : byte absolute $00+$22; // Modulation Control Register
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const
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// ICR
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ICS1 = 2; // Interrupt Sense Control 1 bits
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ISC0 = 0; // Interrupt Sense Control 0 bits
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// MCUCS
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PLUPB = 7; // Pull-up Enable Port B
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SE = 5; // Sleep Enable
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SM = 4; // Sleep Mode
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WDRF = 3; // Watchdog Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACO = 5; // Analog Comparator Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// ICR
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TOIE0 = 4; // Timer/Counter0 Overflow Interrupt Enable
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// IFR
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TOV0 = 4; // Timer/Counter0 Overflow Flag
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// TCCR0
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FOV0 = 7; // Force Overflow
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OOM0 = 3; // Overflow Output Mode, Bits
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CS0 = 0; // Clock Select0 bits
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// WDTCR
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WDTOE = 4; // RW
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WDE = 3; // Watch Dog Enable
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WDP = 0; // Watch Dog Timer Prescaler bits
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// ICR
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INT = 6; // External Interrupt Request 1 Enable
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LLIE = 5; // Low-level Input Interrupt Enable
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// IFR
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INTF = 6; // External Interrupt Flags
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// MODCR
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ONTIM4 = 7; // Modulation On-time Bit 4
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OTIM3 = 6; // Modulation On-time Bit 3
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ONTIM = 3; // Modulation On-time Bits
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MCONF = 0; // Modulation Configuration Bits
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt 1
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procedure LOW_LEVEL_IO_PINS_ISR; external name 'LOW_LEVEL_IO_PINS_ISR'; // Interrupt 3 Low-level Input on Port B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 4 Timer/Counter0 Overflow
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 5 Analog Comparator
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp LOW_LEVEL_IO_PINS_ISR
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rjmp TIMER0_OVF_ISR
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rjmp ANA_COMP_ISR
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{$i start_noram.inc}
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.weak INT0_ISR
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.weak INT1_ISR
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.weak LOW_LEVEL_IO_PINS_ISR
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.weak TIMER0_OVF_ISR
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.weak ANA_COMP_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set LOW_LEVEL_IO_PINS_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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end;
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end.
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