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592df7fa59
that itself, our LLVM code generator can't handle it, and if it did then
afterwards we would have to spill 90% of those register variables again
to make them SSA)
git-svn-id: trunk@44062 -
140 lines
3.9 KiB
ObjectPascal
140 lines
3.9 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for the Risc-V64
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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unit CPUInfo;
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{$i fpcdefs.inc}
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interface
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uses
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globtype;
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type
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bestreal = double;
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{$if FPC_FULLVERSION>20700}
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bestrealrec = TDoubleRec;
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{$endif FPC_FULLVERSION>20700}
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ts32real = single;
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ts64real = double;
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ts80real = extended;
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ts128real = extended;
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ts64comp = comp;
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pbestreal = ^bestreal;
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{ possible supported processors for this target }
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tcputype = (cpu_none,
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cpu_rv64imac,
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cpu_rv64ima,
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cpu_rv64im,
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cpu_rv64i
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);
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tfputype =
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(fpu_none,
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fpu_libgcc,
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fpu_soft,
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fpu_fd
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);
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tcontrollertype =
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(ct_none
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);
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tcontrollerdatatype = record
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controllertypestr, controllerunitstr: string[20];
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cputype: tcputype; fputype: tfputype;
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flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
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end;
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Const
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = false;
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$PUSH}
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{$WARN 3177 OFF}
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
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{$POP}
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{ calling conventions supported by the code generator }
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supported_calling_conventions: tproccalloptions = [
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pocall_internproc,
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pocall_stdcall,
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{ the difference to stdcall is only the name mangling }
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pocall_cdecl,
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{ the difference to stdcall is only the name mangling }
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pocall_cppdecl,
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{ the difference with stdcall is that all const record
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parameters are passed by reference }
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pocall_mwpascal
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];
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cputypestr: array[tcputype] of string[10] = ('',
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'RV64IMAC',
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'RV64IMA',
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'RV64IM',
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'RV64I'
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);
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fputypestr: array[tfputype] of string[8] = (
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'NONE',
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'LIBGCC',
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'SOFT',
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'FD'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_loopunroll,cs_opt_nodecse,
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cs_opt_tailrecursion,cs_opt_reorder_fields,cs_opt_fastmath,
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cs_opt_stackframe];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_nodecse,cs_opt_tailrecursion];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe];
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type
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tcpuflags =
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(CPURV_HAS_MUL,
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CPURV_HAS_ATOMIC,
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CPURV_HAS_COMPACT
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_rv64imac } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT],
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{ cpu_rv64ima } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC],
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{ cpu_rv64im } [CPURV_HAS_MUL],
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{ cpu_rv64i } []
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);
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implementation
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end.
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