sergei 41751bc5b4 + Next portion of MIPS peephole optimizations. Get more aggressive and do more than a single pass if needed, enabling optimization of instructions that logically turn into MOVE due to register renaming. ... git-svn-id: trunk@33095 -		2016-02-13 12:33:30 +00:00
..
aasmcpu.pas	* MIPS: reworked and fixed procedure fixup_jmps:	2016-02-12 13:53:04 +00:00
aoptcpu.pas	+ Next portion of MIPS peephole optimizations. Get more aggressive and do more than a single pass if needed, enabling optimization of instructions that logically turn into MOVE due to register renaming.	2016-02-13 12:33:30 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas
cpubase.pas
cpuelf.pas
cpugas.pas	- MIPS: removed the ugly hack of splitting LDC1/SDC1 instructions into pairs of LWC1/SWC1 at assembler writer level. It probably was there as a workaround for insufficient alignment of double-precision variables, which was present once, but fixed a long time ago.	2016-02-11 15:09:19 +00:00
cpuinfo.pas
cpunode.pas
cpupara.pas
cpupi.pas
cputarg.pas
hlcgcpu.pas
itcpugas.pas
mipsreg.dat
ncpuadd.pas
ncpucall.pas
ncpucnv.pas
ncpuinln.pas
ncpuld.pas
ncpumat.pas
ncpuset.pas
opcode.inc
racpugas.pas	* Don't do useless string case conversions in a loop.	2016-02-10 02:10:23 +00:00
rgcpu.pas
rmipscon.inc
rmipsdwf.inc
rmipsgas.inc
rmipsgri.inc
rmipsgss.inc
rmipsnor.inc
rmipsnum.inc
rmipsrni.inc
rmipssri.inc
rmipssta.inc
rmipsstd.inc
rmipssup.inc
strinst.inc
symcpu.pas