florian b9affc3406 * RiscV64: type conversion to 8 bit improved ... git-svn-id: trunk@49015 -		2021-03-19 17:39:52 +00:00
..
aoptcpu.pas	- RISC-V: Share optimizations between 32 and 64-bit.	2020-01-13 22:49:23 +00:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	* RiscV64: type conversion to 8 bit improved	2021-03-19 17:39:52 +00:00
cpubase.pas	+ RiscV: initial support of pic generation	2021-03-13 16:18:00 +00:00
cpuinfo.pas	* disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does	2020-01-29 22:21:07 +00:00
cpunode.pas
cpupara.pas	* renamed getintparaloc to getcgtempparaloc	2019-12-24 22:12:25 +00:00
cpupi.pas
cputarg.pas	* unified RiscV32 and RiscV64 GAS readers	2021-03-07 08:53:03 +00:00
hlcgcpu.pas	Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux	2020-08-25 13:29:16 +00:00
nrv64add.pas
nrv64cal.pas
nrv64cnv.pas
nrv64ld.pas
nrv64mat.pas	* reworked usage of tcgnotnode.handle_locjump	2020-08-05 21:15:32 +00:00
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
rv32reg.dat
symcpu.pas
tripletcpu.pas	* mark all external assemblers using an LLVM tool using af_llvm	2020-07-19 14:30:35 +00:00