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54 Commits

Author SHA1 Message Date
florian
b9affc3406 * RiscV64: type conversion to 8 bit improved 
git-svn-id: trunk@49015 -
 2021-03-19 17:39:52 +00:00
florian
9ccdf2b3bf * RiscV: unified itcpugas.pas 
git-svn-id: trunk@48960 -
 2021-03-14 10:29:23 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
florian
d1fb44044f * unified RiscV32 and RiscV64 GAS readers 
git-svn-id: trunk@48894 -
 2021-03-07 08:53:03 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888 
git-svn-id: trunk@47103 -
 2020-10-13 19:59:01 +00:00
pierre
d4c9e1f260 Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux 
git-svn-id: trunk@46689 -
 2020-08-25 13:29:16 +00:00
florian
28f25b2df0 * reworked usage of tcgnotnode.handle_locjump 
git-svn-id: trunk@46275 -
 2020-08-05 21:15:32 +00:00
Jonas Maebe
eb7ba1690e * mark all external assemblers using an LLVM tool using af_llvm 
+ added support for constructing target triplets
  * pass "-target triplet" when using an LLVM assembler
   o removed no longer needed $DARWINVERSION and $ARCH parameters
  * consistently use as_clang_gas when clang is used to assembler GAS-style
    assembly, and rename as_llcm_clang to as_clang_llvm (for consistency)
  * support pipe assembling when using clang on *nix in all cases

git-svn-id: trunk@45807 -
 2020-07-19 14:30:35 +00:00
Jonas Maebe
592df7fa59 * disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does 
that itself, our LLVM code generator can't handle it, and if it did then
    afterwards we would have to spill 90% of those register variables again
    to make them SSA)

git-svn-id: trunk@44062 -
 2020-01-29 22:21:07 +00:00
Jeppe Johansen
02c3f328a2 - RISC-V: Share optimizations between 32 and 64-bit. 
git-svn-id: trunk@43934 -
 2020-01-13 22:49:23 +00:00
svenbarth
f59eae4f81 * correctly handle local reference in the RISC V assembler readers (both 32 and 64 bit) 
git-svn-id: trunk@43790 -
 2019-12-25 15:23:28 +00:00
Jonas Maebe
1e3f72403e * renamed getintparaloc to getcgtempparaloc 
o it can be used for more than integer parameters

git-svn-id: trunk@43781 -
 2019-12-24 22:12:25 +00:00
florian
ef87879402 * common naming for fpu_none string 
git-svn-id: trunk@43768 -
 2019-12-24 16:14:28 +00:00
pierre
92b0ea7d02 Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors 
git-svn-id: trunk@43613 -
 2019-11-29 23:26:45 +00:00
pierre
fb33da5f41 Change parameter type to tcgint for is_imm12 and is_lui_imm functions to avoid range check errors 
git-svn-id: trunk@43609 -
 2019-11-29 10:31:31 +00:00
florian
e1e8986462 * patch by J. Gareth Moreton, issue #36271, part 3: support for the other architectures 
git-svn-id: trunk@43441 -
 2019-11-10 16:11:40 +00:00
florian
69786ffe73 somehow committing went wrong, second part of last commit: 
+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers

git-svn-id: trunk@42917 -
 2019-09-03 21:07:33 +00:00
Jeppe Johansen
a1a17447ff - Fix bug in 64bit softfloat double negation. 
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.

git-svn-id: trunk@42335 -
 2019-07-07 11:32:27 +00:00
pierre
828a248287 Systematically include fpcdefs.inc at sart of all units used by compiler 
git-svn-id: trunk@42322 -
 2019-07-03 13:35:05 +00:00
Jonas Maebe
1b6425176b * synchronised with trunk till r42049 
git-svn-id: branches/debug_eh@42050 -
 2019-05-12 18:44:05 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
Jonas Maebe
a0f850d57f * synchronised with trunk till r41885 
git-svn-id: branches/debug_eh@41886 -
 2019-04-16 16:20:44 +00:00
Jeppe Johansen
2b78a8fd3d - Add support for .option directive in riscv assembler. 
- Use addiw when adjusting U32 to S32

git-svn-id: trunk@41870 -
 2019-04-14 20:51:29 +00:00
Jonas Maebe
ac883969a9 * synchronised with trunk till r41423 
git-svn-id: branches/debug_eh@41424 -
 2019-02-23 17:08:03 +00:00
Jonas Maebe
8b9e90dc7a * keep track of whether a routine has a C-style variadic parameter in the 
procoptions even when it's through an array-of-const parameter
  * always call create_varargs_paraloc_info() instead of create_paraloc_info()
    in the former case, even when no varargs parameters are specified (because
    on some platforms even some non-variadic parameters need to be passed
    differently, such as on ARM with gnueabihf)

git-svn-id: trunk@41420 -
 2019-02-23 15:42:45 +00:00
Jonas Maebe
bfc7c58a69 * synchronised with trunk till r40348 
git-svn-id: branches/debug_eh@40349 -
 2018-11-18 12:01:50 +00:00
pierre
53a27fe7b3 Disable range check in m68k:tiscv32 and riscv64 cgcpu units 
git-svn-id: trunk@40319 -
 2018-11-15 16:58:40 +00:00
florian
9b0ff05ee8 - get rid of MaxOps, it is redundant with max_operands 
* MatchOpType with three operands is only available of max_operands>2

git-svn-id: trunk@40190 -
 2018-11-02 21:32:29 +00:00
Jonas Maebe
8555ec1438 + fpc_eh_return_data_regno() intrinsic to get the return register numbers 
for the Dwarf EH exception handler result

git-svn-id: branches/debug_eh@40070 -
 2018-10-28 18:16:38 +00:00
pierre
92acd38f40 Fix for bug report #34380 
git-svn-id: trunk@39986 -
 2018-10-18 20:21:54 +00:00
pierre
aa89182bf5 Fix compilation with -dEXTDEBUG 
git-svn-id: trunk@39923 -
 2018-10-13 11:34:53 +00:00
pierre
68bcffc3e0 Fix riscv64 compiler compilation with -dEXTDEBUG 
git-svn-id: trunk@39922 -
 2018-10-13 09:47:29 +00:00
Jeppe Johansen
d33b520690 Clean up peephole optimization code. 
Add hardfloat ABI option for RiscV. Still needs proper implementation though.
Add CG support for profiling.

git-svn-id: branches/laksen/riscv_new@39798 -
 2018-09-24 17:15:22 +00:00
Jeppe Johansen
8f4173c54d Add a number of optimizations. 
Don't do CSE restructuring when has full evaluation enabled.

git-svn-id: branches/laksen/riscv_new@39781 -
 2018-09-20 20:27:58 +00:00
Jeppe Johansen
74a7963d58 Redo overflow checking code. 
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.

git-svn-id: branches/laksen/riscv_new@39762 -
 2018-09-16 18:37:59 +00:00
Jeppe Johansen
1f68caaf82 Removed reuse of src and dest registers in g_concatcopy as that 
could modify registers used for other stuff(ex. framepointer).

git-svn-id: branches/laksen/riscv_new@39717 -
 2018-09-09 14:02:54 +00:00
florian
f040c19fd6 * cleanup 
git-svn-id: branches/laksen/riscv_new@39712 -
 2018-09-07 19:22:59 +00:00
Jeppe Johansen
29ea4ed07d Add rounding mode operands. 
Add support for trunc and round methods.

git-svn-id: branches/laksen/riscv_new@39698 -
 2018-09-01 19:48:44 +00:00
Jeppe Johansen
f781c8942e Write real atomic operations, and add memory barrier operations. 
Add support for fence, and acquire/release syntax to assembler reader.
Fix broken register aliases.

git-svn-id: branches/laksen/riscv_new@39524 -
 2018-07-29 16:43:09 +00:00
Jeppe Johansen
90d5f5e760 Added library search paths. 
Removed GP and TP from allocatable registers for now. GP should not be overwritten.
Ported dllprt0.as
Fixed register usage in cprt0.as

git-svn-id: branches/laksen/riscv_new@39522 -
 2018-07-29 13:08:15 +00:00
Jeppe Johansen
76dda5813e Updated dynlinker filename. 
Fix passing of vararg register pairs.
Fix passing of big record, and return of records.
Disabled framepointer elimination for the time being.

git-svn-id: branches/laksen/riscv_new@39519 -
 2018-07-28 20:06:06 +00:00
florian
dc3830d78d * integer and float registers do not overlay on Risc-V 
git-svn-id: branches/laksen/riscv_new@39512 -
 2018-07-26 20:57:01 +00:00
Jeppe Johansen
27ab039366 Fixed _fini and _init references in cprt0.as 
Add RiscV to fcl-res and fpcres.
Check that constant is a valid imm12 when doing overflow checking.

git-svn-id: branches/laksen/riscv_new@39494 -
 2018-07-23 11:40:55 +00:00
Jeppe Johansen
b98eb3daa9 Changed order in stack unravelling RTL code, to match the most common cases. 
Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.

git-svn-id: branches/laksen/riscv_new@39492 -
 2018-07-23 01:11:31 +00:00
florian
f3b7e3281a * fix int to real for non-register locations 
git-svn-id: branches/laksen/riscv_new@39491 -
 2018-07-22 20:48:15 +00:00
Jeppe Johansen
6d9a0fdc73 Added implementation of InstructionLoadsFromReg. 
Fixed spilling_get_operation_type_ref, no mem operation modifies ref registers.

git-svn-id: branches/laksen/riscv_new@39487 -
 2018-07-22 18:38:07 +00:00
Jeppe Johansen
a906feb05e Fixed bug in peephole optimizer. 
git-svn-id: branches/laksen/riscv_new@39486 -
 2018-07-22 16:58:10 +00:00
Jeppe Johansen
2499129ba5 Pass aggregates larger than 2*XLEN as a reference. 
Fix load_reg_reg and make it do proper type conversions.
Added maybeadjust to tcgrv.

git-svn-id: branches/laksen/riscv_new@39485 -
 2018-07-22 14:15:29 +00:00
florian
9776ea2afe * SLTIU -> SLTU 
git-svn-id: branches/laksen/riscv_new@39484 -
 2018-07-22 13:55:53 +00:00
florian
65a415c13e * fix assembling with official binutils 
* fix compilation on 32 bit hosts
+ compile with -Sew

git-svn-id: branches/laksen/riscv_new@39482 -
 2018-07-22 13:10:24 +00:00