florian b2f5f6ac7d + RiscV32: use sext.b if available		2025-02-24 23:05:49 +01:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	+ RiscV32: use sext.b if available	2025-02-24 23:05:49 +01:00
cpuinfo.pas	+ RiscV: rv32gcb	2025-02-22 21:57:52 +01:00
cpunode.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
cpupara.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nrv32add.pas
nrv32cal.pas
nrv32cnv.pas
nrv32mat.pas	Fix compilation of riscv32 compiler	2025-01-10 12:10:02 +00:00
nrv32util.pas	* fixes RiscV32 building	2024-12-25 22:48:40 +01:00
rrv32con.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32dwa.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32nor.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32num.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32rni.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sri.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sta.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32std.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sup.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
symcpu.pas
tripletcpu.pas