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https://gitlab.com/freepascal.org/fpc/source.git
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ecfbbeffc3
* renamed registers32 to registersint * replace some s32bit,u32bit with torddef([su]inttype).def.typ
263 lines
9.6 KiB
ObjectPascal
263 lines
9.6 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate ARM assembler for type converting nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmcnv;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncnv,ncgcnv,defcmp;
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type
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tarmtypeconvnode = class(tcgtypeconvnode)
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protected
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function first_int_to_real: tnode;override;
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{ procedure second_int_to_int;override; }
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{ procedure second_string_to_string;override; }
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{ procedure second_cstring_to_pchar;override; }
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{ procedure second_string_to_chararray;override; }
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{ procedure second_array_to_pointer;override; }
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// function first_int_to_real: tnode; override;
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{ procedure second_pointer_to_array;override; }
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{ procedure second_chararray_to_string;override; }
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{ procedure second_char_to_string;override; }
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procedure second_int_to_real;override;
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// procedure second_real_to_real;override;
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{ procedure second_cord_to_pointer;override; }
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{ procedure second_proc_to_procvar;override; }
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{ procedure second_bool_to_int;override; }
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procedure second_int_to_bool;override;
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{ procedure second_load_smallset;override; }
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{ procedure second_ansistring_to_pchar;override; }
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{ procedure second_pchar_to_string;override; }
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{ procedure second_class_to_intf;override; }
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{ procedure second_char_to_char;override; }
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end;
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implementation
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uses
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verbose,globals,systems,
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symconst,symdef,aasmbase,aasmtai,
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defutil,
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cgbase,pass_1,pass_2,
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ncon,ncal,
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ncgutil,
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cpubase,aasmcpu,
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rgobj,tgobj,cgobj,cgcpu;
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{*****************************************************************************
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FirstTypeConv
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*****************************************************************************}
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function tarmtypeconvnode.first_int_to_real: tnode;
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var
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fname: string[19];
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begin
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{ converting a 64bit integer to a float requires a helper }
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if is_64bitint(left.resulttype.def) then
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begin
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if is_signed(left.resulttype.def) then
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fname := 'fpc_int64_to_double'
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else
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fname := 'fpc_qword_to_double';
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result := ccallnode.createintern(fname,ccallparanode.create(
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left,nil));
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left:=nil;
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firstpass(result);
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exit;
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end
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else
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{ other integers are supposed to be 32 bit }
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begin
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if is_signed(left.resulttype.def) then
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inserttypeconv(left,s32inttype)
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else
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inserttypeconv(left,u32inttype);
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firstpass(left);
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end;
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result := nil;
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if registersfpu<1 then
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registersfpu:=1;
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expectloc:=LOC_FPUREGISTER;
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end;
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procedure tarmtypeconvnode.second_int_to_real;
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var
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instr : taicpu;
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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location_force_reg(exprasmlist,left.location,OS_32,true);
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location.register:=cg.getfpuregister(exprasmlist,location.size);
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instr:=taicpu.op_reg_reg(A_FLT,location.register,left.location.register);
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instr.oppostfix:=cgsize2fpuoppostfix[def_cgsize(resulttype.def)];
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exprasmlist.concat(instr);
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end;
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procedure tarmtypeconvnode.second_int_to_bool;
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var
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hregister : tregister;
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href : treference;
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resflags : tresflags;
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hlabel,oldtruelabel,oldfalselabel : tasmlabel;
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begin
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oldtruelabel:=truelabel;
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oldfalselabel:=falselabel;
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objectlibrary.getlabel(truelabel);
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objectlibrary.getlabel(falselabel);
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secondpass(left);
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if codegenerror then
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exit;
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{ byte(boolean) or word(wordbool) or longint(longbool) must
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be accepted for var parameters }
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if (nf_explicit in flags) and
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(left.resulttype.def.size=resulttype.def.size) and
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(left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE,LOC_CREGISTER]) then
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begin
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location_copy(location,left.location);
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truelabel:=oldtruelabel;
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falselabel:=oldfalselabel;
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exit;
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end;
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{ Load left node into flag F_NE/F_E }
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resflags:=F_NE;
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case left.location.loc of
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LOC_CREFERENCE,
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LOC_REFERENCE :
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begin
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if left.location.size in [OS_64,OS_S64] then
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begin
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location_release(exprasmlist,left.location);
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hregister:=cg.getintregister(exprasmlist,OS_INT);
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cg.a_load_ref_reg(exprasmlist,OS_32,OS_32,left.location.reference,hregister);
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href:=left.location.reference;
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inc(href.offset,4);
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cg.ungetregister(exprasmlist,hregister);
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tcgarm(cg).setflags:=true;
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cg.a_op_ref_reg(exprasmlist,OP_OR,OS_32,href,hregister);
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tcgarm(cg).setflags:=false;
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end
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else
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begin
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location_force_reg(exprasmlist,left.location,left.location.size,true);
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location_release(exprasmlist,left.location);
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tcgarm(cg).setflags:=true;
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cg.a_op_reg_reg(exprasmlist,OP_OR,left.location.size,left.location.register,left.location.register);
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tcgarm(cg).setflags:=false;
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end;
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end;
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LOC_FLAGS :
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begin
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resflags:=left.location.resflags;
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end;
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LOC_REGISTER,LOC_CREGISTER :
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begin
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if left.location.size in [OS_64,OS_S64] then
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begin
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hregister:=cg.getintregister(exprasmlist,OS_32);
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cg.a_load_reg_reg(exprasmlist,OS_32,OS_32,left.location.registerlow,hregister);
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cg.ungetregister(exprasmlist,hregister);
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location_release(exprasmlist,left.location);
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tcgarm(cg).setflags:=true;
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cg.a_op_reg_reg(exprasmlist,OP_OR,OS_32,left.location.registerhigh,hregister);
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tcgarm(cg).setflags:=false;
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end
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else
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begin
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location_release(exprasmlist,left.location);
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tcgarm(cg).setflags:=true;
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cg.a_op_reg_reg(exprasmlist,OP_OR,left.location.size,left.location.register,left.location.register);
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tcgarm(cg).setflags:=false;
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end;
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end;
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LOC_JUMP :
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begin
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hregister:=cg.getintregister(exprasmlist,OS_INT);
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objectlibrary.getlabel(hlabel);
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cg.a_label(exprasmlist,truelabel);
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cg.a_load_const_reg(exprasmlist,OS_INT,1,hregister);
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cg.a_jmp_always(exprasmlist,hlabel);
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cg.a_label(exprasmlist,falselabel);
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cg.a_load_const_reg(exprasmlist,OS_INT,0,hregister);
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cg.a_label(exprasmlist,hlabel);
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cg.ungetregister(exprasmlist,hregister);
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tcgarm(cg).setflags:=true;
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cg.a_op_reg_reg(exprasmlist,OP_OR,OS_INT,hregister,hregister);
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tcgarm(cg).setflags:=false;
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end;
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else
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internalerror(200311301);
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end;
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{ load flags to register }
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location_reset(location,LOC_REGISTER,def_cgsize(resulttype.def));
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location.register:=cg.getintregister(exprasmlist,location.size);
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cg.g_flags2reg(exprasmlist,location.size,resflags,location.register);
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truelabel:=oldtruelabel;
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falselabel:=oldfalselabel;
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end;
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begin
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ctypeconvnode:=tarmtypeconvnode;
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end.
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{
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$Log$
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Revision 1.9 2004-02-03 22:32:54 peter
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* renamed xNNbittype to xNNinttype
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* renamed registers32 to registersint
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* replace some s32bit,u32bit with torddef([su]inttype).def.typ
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Revision 1.8 2004/01/22 20:13:18 florian
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* fixed several issues with flags
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Revision 1.7 2003/11/30 19:35:29 florian
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* fixed several arm related problems
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Revision 1.6 2003/11/04 22:30:15 florian
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+ type cast variant<->enum
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* cnv. node second pass uses now as well helper wrappers
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Revision 1.5 2003/11/02 14:30:03 florian
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* fixed ARM for new reg. allocation scheme
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Revision 1.4 2003/09/01 15:11:16 florian
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* fixed reference handling
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* fixed operand postfix for floating point instructions
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* fixed wrong shifter constant handling
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Revision 1.3 2003/09/01 09:54:57 florian
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* results of work on arm port last weekend
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Revision 1.2 2003/08/25 23:20:38 florian
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+ started to implement FPU support for the ARM
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* fixed a lot of other things
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Revision 1.1 2003/08/21 23:24:08 florian
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* continued to work on the arm skeleton
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}
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