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9376f5a43a
fpc/compiler/aarch64
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Jonas Maebe 9376f5a43a * AArch64: added SIMD instructions (only plain ARMv8-A for now) 
o added AArch64 regset parsing support in assembler reader, means that "{"
     no longer starts comments there (like in the ARM assembler reader)
   o added AArch64 indexed SIMD register support and removed old cg hacks
     that worked around its absence

git-svn-id: trunk@47116 -
2020-10-15 20:29:36 +00:00
..
a64att.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
a64atts.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
a64ins.dat * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
a64nop.inc
a64op.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
a64reg.dat * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
a64tab.inc * corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by 2015-05-14 14:42:12 +00:00
aasmcpu.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
agcpugas.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
aoptcpu.pas * patch (with little modification) by J. Gareth Moreton: refactor ARM/Aarch64 peephole optimizer, first part of #37526 2020-09-27 21:05:42 +00:00
aoptcpub.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
aoptcpud.pas
cgcpu.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
cpubase.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
cpuinfo.pas * disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does 2020-01-29 22:21:07 +00:00
cpunode.pas + implement compiler support for SEH on Win64 2020-04-21 06:06:05 +00:00
cpupara.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
cpupi.pas + implement compiler support for SEH on Win64 2020-04-21 06:06:05 +00:00
cputarg.pas + implement initial compiler support for Win64 on Aarch64 2020-04-21 06:04:22 +00:00
hlcgcpu.pas * patch by Marģers to unify internal error numbers, resolves #37888 2020-10-13 19:59:01 +00:00
itcpugas.pas
ncpuadd.pas + support for software floating point exception handling on AArch64 (-CE) 2019-09-01 17:26:11 +00:00
ncpucnv.pas * Removed unused local vars. 2018-11-02 18:44:29 +00:00
ncpucon.pas * avoid that -0.0 is handled by the eor optimization 2019-09-04 20:45:24 +00:00
ncpuflw.pas * patch by Marģers to unify internal error numbers, resolves #37888 2020-10-13 19:59:01 +00:00
ncpuinl.pas + support for software floating point exception handling on AArch64 (-CE) 2019-09-01 17:26:11 +00:00
ncpumat.pas * reworked usage of tcgnotnode.handle_locjump 2020-08-05 21:15:32 +00:00
ncpumem.pas * keep track of the temp position separately from the offset in references, 2018-04-22 17:03:16 +00:00
ncpuset.pas * generate jump tables into the same section as the code as otherwise we'll get bogus relocations (in case of clang.exe) or a future support for armasm64.exe will reject the relative symbols outright 2020-04-21 06:06:36 +00:00
ra64con.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64dwa.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64nor.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64num.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64rni.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64sri.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64sta.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64std.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
ra64sup.inc * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
racpu.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
racpugas.pas * AArch64: added SIMD instructions (only plain ARMv8-A for now) 2020-10-15 20:29:36 +00:00
rgcpu.pas + Aarch64: trgcpu.get_spill_subreg: return MM sub register correctly, resolves #37393 2020-07-20 21:07:09 +00:00
symcpu.pas o fixes handling of iso i/o parameters/program parameters: 2015-05-01 20:58:31 +00:00
tripletcpu.pas * mark all external assemblers using an LLVM tool using af_llvm 2020-07-19 14:30:35 +00:00