florian 971d97c179 + RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0		2025-01-11 21:03:54 +01:00
..
aoptcpu.pas	* do no generated debug comment in assembler output of RiscV if not requested	2024-05-25 20:16:42 +02:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests	2024-12-22 22:37:16 +01:00
cpuinfo.pas	+ more RiscV extensions	2024-11-17 15:05:35 +01:00
cpunode.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
cpupara.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nrv64add.pas
nrv64cal.pas
nrv64cnv.pas
nrv64ld.pas
nrv64mat.pas	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
rrv64con.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64dwa.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64nor.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64num.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64rni.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sri.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sta.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64std.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv64sup.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
symcpu.pas
tripletcpu.pas