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aoptcpu.pas
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+ take into account the fact that lea doesn't read the segment register of its
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2017-05-04 14:13:53 +00:00 |
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aoptcpub.pas
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* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same
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2016-04-21 20:14:01 +00:00 |
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aoptcpud.pas
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* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same
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2016-04-21 20:14:01 +00:00 |
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cgcpu.pas
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* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr
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2017-04-19 21:30:31 +00:00 |
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cpubase.inc
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cpuelf.pas
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Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen).
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2014-12-14 16:28:35 +00:00 |
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cpuinfo.pas
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+ added 486 to the list of supported CPUs on the i8086 and i386 targets
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2016-03-23 15:07:56 +00:00 |
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cpunode.pas
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* automatically generate necessary indirect symbols when a new assembler
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2016-07-20 20:53:03 +00:00 |
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cpupara.pas
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* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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2017-02-25 11:46:35 +00:00 |
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cpupi.pas
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* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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2016-12-16 22:41:21 +00:00 |
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cputarg.pas
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merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run.
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2014-08-17 18:18:07 +00:00 |
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hlcgcpu.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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i386att.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386atts.inc
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* x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:
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2016-11-21 02:07:13 +00:00 |
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i386int.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386nop.inc
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* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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2016-11-21 13:59:44 +00:00 |
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i386op.inc
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+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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2016-11-18 20:19:39 +00:00 |
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i386prop.inc
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+ precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions
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2017-05-05 13:41:43 +00:00 |
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i386tab.inc
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* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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2016-11-21 13:59:44 +00:00 |
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n386add.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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n386cal.pas
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syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed
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2016-12-02 09:29:09 +00:00 |
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n386flw.pas
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+ added volatility information to all memory references
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2016-11-27 18:17:37 +00:00 |
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n386inl.pas
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n386ld.pas
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* factored out the loading of threadvars in its own method, and put the
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2015-09-12 23:32:53 +00:00 |
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n386mat.pas
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* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr
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2017-04-19 21:30:31 +00:00 |
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n386mem.pas
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n386set.pas
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r386ari.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386att.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386con.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386dwrf.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386int.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386iri.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386nasm.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386nor.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386nri.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386num.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386ot.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386rni.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386sri.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386stab.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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r386std.inc
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+ added individual bits of the x86 flags register as subregisters
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2017-04-26 13:52:52 +00:00 |
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ra386att.pas
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ra386int.pas
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rgcpu.pas
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symcpu.pas
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* changed getpointerdef() into a tpointerdef.getreusable() class method
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2015-06-22 08:17:49 +00:00 |
