mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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4686f61002
so that they can still be freed after the reference has been changed
(e.g. in case of array indexing or record field accesses) (mantis #33628)
git-svn-id: trunk@38814 -
209 lines
7.8 KiB
ObjectPascal
209 lines
7.8 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the code generator for the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,parabase,
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cgbase,cgutils,cgobj,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cpubase,cpuinfo,
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node,symconst,SymType,symdef,
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rgcpu,
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cgsparc;
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type
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TCGSparc64=class(TCGSparcGen)
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procedure a_load_reg_reg(list : TAsmList; fromsize,tosize : tcgsize; reg1,reg2 : tregister);override;
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procedure a_load_ref_reg_unaligned(list : TAsmList; fromsize,tosize : tcgsize; const ref : treference; register : tregister);override;
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procedure a_load_reg_ref_unaligned(list : TAsmList; fromsize,tosize : tcgsize; register : tregister; const ref : treference);override;
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procedure a_load_const_reg(list : TAsmList; size : TCGSize; a : tcgint; reg : TRegister);override;
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end;
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procedure create_codegen;
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implementation
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uses
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verbose,
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systems;
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procedure TCGSparc64.a_load_reg_reg(list:TAsmList;fromsize,tosize:tcgsize;reg1,reg2:tregister);
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var
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instr : taicpu;
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begin
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if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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((tcgsize2size[fromsize] = tcgsize2size[tosize]) and
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(fromsize <> tosize)) or
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{ needs to mask out the sign in the top 16 bits }
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((fromsize = OS_S8) and
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(tosize = OS_16)) then
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case tosize of
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OS_8 :
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list.concat(taicpu.op_reg_const_reg(A_AND,reg1,$ff,reg2));
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OS_16 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLLX,reg1,48,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRLX,reg2,48,reg2));
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end;
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OS_32 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLLX,reg1,32,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRLX,reg2,32,reg2));
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end;
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OS_S32 :
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list.concat(taicpu.op_reg_reg_reg(A_SRA,reg1,NR_G0,reg2));
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OS_64,
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OS_S64 :
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begin
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instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
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list.Concat(instr);
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{ Notify the register allocator that we have written a move instruction so
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it can try to eliminate it. }
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add_move_instruction(instr);
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end;
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OS_S8 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLLX,reg1,56,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRAX,reg2,56,reg2));
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end;
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OS_S16 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLLX,reg1,48,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRAX,reg2,48,reg2));
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end;
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else
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internalerror(2017060501);
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end
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else
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begin
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instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
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list.Concat(instr);
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{ Notify the register allocator that we have written a move instruction so
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it can try to eliminate it. }
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add_move_instruction(instr);
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end;
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end;
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procedure TCGSparc64.a_load_ref_reg_unaligned(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; register: tregister);
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var
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href: treference;
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hreg1, hreg2, tmpreg: tregister;
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begin
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if fromsize in [OS_64,OS_S64] then
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begin
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{ split into two 32 bit loads }
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hreg1:=getintregister(list,OS_32);
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hreg2:=getintregister(list,OS_32);
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a_load_ref_reg(list,OS_32,OS_32,ref,hreg1);
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href:=ref;
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inc(href.offset,4);
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a_load_ref_reg(list,OS_32,OS_32,href,hreg2);
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a_op_const_reg_reg(list,OP_SHL,OS_64,32,hreg1,register);
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a_op_reg_reg_reg(list,OP_OR,OS_64,hreg2,register,register);
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end
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else
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inherited;
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end;
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procedure TCGSparc64.a_load_reg_ref_unaligned(list : TAsmList;fromsize,tosize : tcgsize;register : tregister;const ref : treference);
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var
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href: treference;
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hreg1: tregister;
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begin
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if fromsize in [OS_64,OS_S64] then
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begin
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{ split into two 32 bit stores }
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href:=ref;
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if not(TCGSparc64(cg).IsSimpleRef(href)) then
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begin
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hreg1:=getintregister(list,OS_ADDR);
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a_loadaddr_ref_reg(list,href,hreg1);
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reference_reset_base(href,hreg1,0,href.temppos,href.alignment,href.volatility);
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end;
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inc(href.offset,4);
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a_load_reg_ref(list,OS_32,OS_32,register,href);
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hreg1:=getintregister(list,OS_32);
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a_op_const_reg_reg(list,OP_SHR,OS_64,32,register,hreg1);
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dec(href.offset,4);
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a_load_reg_ref(list,OS_32,OS_32,hreg1,href);
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end
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else
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inherited;
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end;
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procedure TCGSparc64.a_load_const_reg(list : TAsmList;size : TCGSize;a : tcgint;reg : TRegister);
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var
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hreg : TRegister;
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begin
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{ we don't use the set instruction here because it could be evalutated to two
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instructions which would cause problems with the delay slot (FK) }
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if a=0 then
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list.concat(taicpu.op_reg(A_CLR,reg))
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else if (a>=simm13lo) and (a<=simm13hi) then
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list.concat(taicpu.op_const_reg(A_MOV,a,reg))
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else if (a>=0) and (a<=$ffffffff) then
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begin
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list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg));
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if (aint(a) and aint($3ff))<>0 then
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list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
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end
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else if (a>=-4294967296) and (a<=-1) then
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begin
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list.concat(taicpu.op_const_reg(A_SETHI,(not(aint(a)) shr 10) and $3fffff,reg));
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if (aint(a) and aint($3ff)) or aint($1c00)<>0 then
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list.concat(taicpu.op_reg_const_reg(A_XOR,reg,(aint(a) and aint($3ff)) or aint($1c00),reg));
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end
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else
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begin
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hreg:=getintregister(list,OS_64);
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list.concat(taicpu.op_const_reg(A_SETHI,(aint(a) shr 10) and $3fffff,reg));
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list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 42,hreg));
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if ((aint(a) shr 32) and aint($3ff))<>0 then
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list.concat(taicpu.op_reg_const_reg(A_OR,hreg,(aint(a) shr 32) and aint($3ff),hreg));
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if (aint(a) and aint($3ff))<>0 then
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list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
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a_op_const_reg_reg(list,OP_SHL,OS_64,32,hreg,hreg);
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list.concat(taicpu.op_reg_reg_reg(A_OR,reg,hreg,reg));
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end;
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end;
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procedure create_codegen;
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begin
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cg:=TCgSparc64.Create;
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if target_info.system=system_sparc64_linux then
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TCgSparc64(cg).use_unlimited_pic_mode:=true
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else
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TCgSparc64(cg).use_unlimited_pic_mode:=false;
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cg128:=tcg128.create;
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end;
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end.
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