Interferon c482bafdaf There is code in the register allocator to restrict register allocation to the ... first 16 registers in RISC-V RVE and RVEC modes. However, there was still code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation of up to register X17 in RVE and RVEC modes. Modified this function to take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes. Also put conditional code in setjump.inc assembler code to only set the first 16 registers in RVE and RVEC modes. The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.		2023-08-26 22:12:00 +02:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	riscv32: Fix 64bit comparisons	2022-10-16 17:37:53 +02:00
cpuinfo.pas	There is code in the register allocator to restrict register allocation to the	2023-08-26 22:12:00 +02:00
cpunode.pas
cpupara.pas	There is code in the register allocator to restrict register allocation to the	2023-08-26 22:12:00 +02:00
cpupi.pas
cputarg.pas	+ first work for esp32-c3 support	2023-01-28 21:28:19 +01:00
hlcgcpu.pas
nrv32add.pas	riscv32: Fix 64bit comparisons	2022-10-16 17:37:53 +02:00
nrv32cal.pas
nrv32cnv.pas
nrv32mat.pas
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
symcpu.pas
tripletcpu.pas