nickysn e6a4435330 + support the aitconst_XXbit_unaligned const types in the NASM asm writer. This ... fixes DWARF support when using NASM. git-svn-id: trunk@25866 -		2013-10-27 15:21:30 +00:00
..
aasmcpu.pas	+ added the NEC V20/V30 instructions	2013-10-11 21:27:56 +00:00
agx86att.pas	* workaround for bug in Apple's assembler regarding movq/vmovq and integer	2013-09-02 14:39:26 +00:00
agx86int.pas
agx86nsm.pas	+ support the aitconst_XXbit_unaligned const types in the NASM asm writer. This	2013-10-27 15:21:30 +00:00
cga.pas
cgx86.pas	* in tcgx86.make_simple_ref, on the i8086, emit 'mov es, reg', instead of	2013-10-06 19:52:38 +00:00
cpubase.pas	+ added function cpubase.segment_regs_equal, which checks whether 2 segment regs are equal in the current memory model	2013-06-23 11:27:00 +00:00
hlcgx86.pas
itcpugas.pas
itx86int.pas
nx86add.pas	* tx86addnode.second_cmpfloat: use getresflags() to reduce code duplication.	2013-09-09 11:25:49 +00:00
nx86cal.pas
nx86cnv.pas	* basic avx support for floating point operations (use -Cfavx to activate)	2013-06-14 20:03:01 +00:00
nx86con.pas
nx86inl.pas	* handle LOC_*FPUREGISTER correctly when using sse2 sqr, resolve #26408	2013-06-16 18:48:08 +00:00
nx86mat.pas	* basic avx support for floating point operations (use -Cfavx to activate)	2013-06-14 20:03:01 +00:00
nx86mem.pas
nx86set.pas	* tx86casenode.genjumptable: explicitly emit near pointers in the case jump table on i8086, regardless of the memory model	2013-09-16 19:58:45 +00:00
rax86.pas
rax86att.pas
rax86int.pas	* convert i8086 inline asm instruction 'call symbol' to 'call far symbol' in memory models with far code	2013-09-08 16:34:12 +00:00
rgx86.pas	* basic avx support for floating point operations (use -Cfavx to activate)	2013-06-14 20:03:01 +00:00
x86ins.dat	- rm LEA reg,imm from x86ins.dat, as that's not a valid x86 instruction,	2013-10-18 23:26:58 +00:00
x86reg.dat	* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.	2013-10-03 08:08:04 +00:00