Jonas Maebe c9de3b2ecd * use the zero register for a_load_const_ref(0) ... git-svn-id: trunk@29960 -		2015-02-23 22:55:29 +00:00
..
a64att.inc	* added some missing instructions and aliases, reordered them according	2015-02-23 22:48:24 +00:00
a64atts.inc	* added some missing instructions and aliases, reordered them according	2015-02-23 22:48:24 +00:00
a64ins.dat	* added some missing instructions and aliases, reordered them according	2015-02-23 22:48:24 +00:00
a64nop.inc	+ instruction table generator for arm64	2012-11-01 16:11:19 +00:00
a64op.inc	* added some missing instructions and aliases, reordered them according	2015-02-23 22:48:24 +00:00
a64reg.dat	* fixed debug register values for vector registers	2015-02-23 22:54:15 +00:00
a64tab.inc	+ instruction table generator for arm64	2012-11-01 16:11:19 +00:00
aasmcpu.pas	+ support for @page and @pageoffs addressing on AArch64: these are PIC	2015-02-23 22:53:43 +00:00
agcpugas.pas	* temporary workaround for writing INS/UMOV operands, as these require	2015-02-23 22:55:14 +00:00
aoptcpu.pas	+ assembler optimizer unit skeleton	2012-11-01 20:09:12 +00:00
aoptcpub.pas	* completed TAoptBaseCpu.RegModifiedByInstruction()	2015-02-23 22:53:23 +00:00
aoptcpud.pas	+ assembler optimizer unit skeleton	2012-11-01 20:09:12 +00:00
cgcpu.pas	* use the zero register for a_load_const_ref(0)	2015-02-23 22:55:29 +00:00
cpubase.pas	* fixed flags_to_cond() and inverse_cond() for C_GE	2015-02-23 22:55:11 +00:00
cpuinfo.pas	* removed ARM copy/paste stuff	2015-02-23 22:55:17 +00:00
cpunode.pas	* switched to using the stack pointer as base register for the temp allocator	2015-02-23 22:54:03 +00:00
cpupara.pas	* pass managed function result addresses as a hidden first parameter instead	2015-02-23 22:55:08 +00:00
cpupi.pas	* switched to using the stack pointer as base register for the temp allocator	2015-02-23 22:54:03 +00:00
cputarg.pas	+ AArch64 cputarg	2015-02-23 22:52:39 +00:00
hlcgcpu.pas	+ dummy AArch64 hlcgcpu	2015-02-23 22:52:14 +00:00
itcpugas.pas	+ ARM64 GAS instruction table unit	2012-11-01 20:09:47 +00:00
ncpuadd.pas	+ initial implementation of aarch64 add nodes	2015-02-23 22:50:07 +00:00
ncpucnv.pas	+ override second_int_to_bool(), because the generic version assumes that	2015-02-23 22:54:09 +00:00
ncpuinl.pas	* switched to using the stack pointer as base register for the temp allocator	2015-02-23 22:54:03 +00:00
ncpumat.pas	+ aarch64 math nodes implementation	2015-02-23 22:50:13 +00:00
ncpumem.pas	* switched to using the stack pointer as base register for the temp allocator	2015-02-23 22:54:03 +00:00
ra64con.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64dwa.inc	* fixed debug register values for vector registers	2015-02-23 22:54:15 +00:00
ra64nor.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64num.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64rni.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64sri.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64sta.inc	* fixed debug register values for vector registers	2015-02-23 22:54:15 +00:00
ra64std.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
ra64sup.inc	+ FPCR, FPSR and TPIDR registers	2015-02-23 22:50:44 +00:00
racpu.pas	+ Aarch64 assembler reader	2015-02-23 22:52:36 +00:00
racpugas.pas	+ support for @page and @pageoffs addressing on AArch64: these are PIC	2015-02-23 22:53:43 +00:00
rgcpu.pas	* add restrictions for loaded/stored registers in case of references	2015-02-23 22:55:23 +00:00
symcpu.pas	Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".	2014-04-11 14:30:59 +00:00